FSK Demodulator using a PLL

[Javier Manzano]

Hi guys,

The issue is I am trying to build, as I said in the topic, an FSK demodulator. Up until now I have most of the circuit: I built a Wien bridge oscillator (the signal I want to demodulate) and the overall PLL with a 555 timer. The issue is I now wanted to make the input vary from 0 to 5Vp in order to have it demodulated, but I don't know how to do it. What kind of circuit am I looking for?

Thanks!

PS: This is my current circuit.

 

[Javier Manzano]

I've been doing some research along the afternoon as it's possible that I haven't really understood the issue here, guys. Not sure if it even makes sense what I wrote lol

This is what they require:

"In this lab session, the student must be able to show the complete operation of the proposed system (Fig. below). In this case, the input to the PLL is the output of block 1 (oscillator), where now the frequency of the oscillator must be programmed using a "tandem" potentiometer (frequency range: 8kHz - 18kHz).

Once the behavior of system composed by Oscilaltor and PLL has been checked, student must use the PLL to demodulate a FSK signal. For this part, the lab signal generator will be used as FSK input signal to the PLL. And the demodulated output must be formed between 0 and 5Vp. For this step an extra circuit must be built to accommodate the output of the PLL to the specification of 5Vp."

 

[Javier Manzano]

Ok, I think I just understood it, sorry for the multiple posts, I just thought I'd give my solution so that people could read it afterwards

Correct me if I'm mistaken, but the PLL itself demodulates the signal and what they require from me is just to pull up the output voltage to 5V, is that right?

Eventhough that image is in Spanish, it's fairly easy to read: first there is the phase detector, then a filter, an amplifier and the VCO. The thing is the output, that is the demodulated signal, comes out of the amplifier. It starts to be "correct" once the PLL locks in, true? It's actually taken me a ton of time to get here... I guess I need to do my maths to finish understanding all this though.

 

[DonT2012]

For FSK demodulation I suspect you would want the loop to distinguish between two different frequencies that are in the lock range of your PLL. One of the two frequencies represents a logical 0 and the other frequency represents a logical 1. The output of the loop just re-produces the input frequency with some phase shift. Each time the input frequency changes, the loop will relock onto the new frequency. The voltage input to the VCO has the frequency info that you need (this is your demodulated signal). This should alternate between two voltages representing the two frequencies, but not necessarily 0V and 5V. So it sounds like you will need to do some filtering to clean up the signal and some level shifting to get it swing between 0V and 5V... Don

 

[GPG]

An xor will work best if both signals are 1:1 mark/space. You can achieve this by dividing them both by 2 eg cd4013 or similar But whether you can depends on the actual carrier frequencies and the data rate. Whether the shift is phase continuous also matters.

 

[dorke]

Javier ,
This can be very helpful:
FSK Modulation and Demodulation using CD74HC4046A

 

[Javier Manzano]

Javier ,
This can be very helpful:
FSK Modulation and Demodulation using CD74HC4046A

Thanks dorke!

I failed the lab anyways. I got the schematic well, but I didn't implement it... well, even worse, I failed to connect the cable to the source. I realised after cleaning up my workspace that I hadn't peeled one of the cables and, obviously, the OA weren't receiving current LOL.

 

[GPG]

The original CD4046
http://www.nxp.com/documents/data_sheet/HEF4046B.pdf