Frequency multiplier x100 for a frequency sweep from 500Hz to 4,5kHz

[ElCapitano]

Good day. I need an easy design for a frequency multiplier x100 to
drive a switched capacitor (SC) Bandpass-Filter.
The problem is (perhaps it isn´t a problem?) that the input frequency
will sweep between 500Hz up to 4,5kHz. I thought about using a PLL
with a divider by 100 between the VCO and the pase comparator. My
first steps with a LM565 PLL went wrong because I only know the PLL
basics and don´t know much about how to design a PLL ckt right.
What´s the point about free running frequency of the VCO? Do I have to
set it so a special frequency that the ckt will work fine? Are there
other possibilities to multiply a frequency x100? Can anyone help me?

Greets
ElCapitano

 

[Rene Tschaggelar]

Good day. I need an easy design for a frequency multiplier x100 to
drive a switched capacitor (SC) Bandpass-Filter.
The problem is (perhaps it isn´t a problem?) that the input frequency
will sweep between 500Hz up to 4,5kHz. I thought about using a PLL
with a divider by 100 between the VCO and the pase comparator. My
first steps with a LM565 PLL went wrong because I only know the PLL
basics and don´t know much about how to design a PLL ckt right.
What´s the point about free running frequency of the VCO? Do I have to
set it so a special frequency that the ckt will work fine? Are there
other possibilities to multiply a frequency x100? Can anyone help me?

Yes.
Various manufacturers of PLLs have plenty of documentation about
'me ande the PLL' to datasheets and simulation programs.

A VCO has a range, say from 10 to 20MHz, usually octave for the
filtering. In your case you need something wider. Have a look at
the LT6900, it does 1kHz to 20MHz in a few ranges.

Another option, if you have the choice to generate the sweep
frequency yourself is a DDS, which generates the 100x frequency
which is subsequently divided down.

Rene

 

[Winfield Hill]

Rene Tschaggelar wrote...

A VCO has a range, say from 10 to 20MHz, usually octave for the
filtering. In your case you need something wider. Have a look at
the LT6900, it does 1kHz to 20MHz in a few ranges.

ElCapitano, the popular 4046 series of PLL chips easily span a
20:1 range, or more. The IC manufacturers have good app notes,
and some even offer free design software, as Rene pointed out.
Design the loop compensation slow enough for use at 500Hz, and
set the maximum frequency at say 7.5kHz, for safety. The chips
to consider are the CD4046 (for supply voltages of 5 to 15V) and
the 74HC4046 (for 3 to 5V logic).

RCA, which eventually became Intersil, created the 4046. But
Intersil has discontinued it and removed the application notes
from its web site. Fairchild took over many of Intersil's ICs,
and offers the chip, but they don't have the original 4046 app
note online. :>(

We have a good section on 4046 PLL design and compensation in
AoE, you could borrow a copy. TI has a few good 4046 app notes,
http://www-s.ti.com/sc/psheets/scha002a/scha002a.pdf
http://www-s.ti.com/sc/psheets/scha003b/scha003b.pdf

And ON Semi, who took over Motorola's CMOS logic, has an appnote
(Motorola was RCA's original competitor),
http://www.onsemi.com/pub/Collateral/AN1410-D.PDF

Philips, who created improved versions of the chip, has lots of
good information on their advanced versions. They also used to
offer a free download design program.

Thanks,
- Win

whill_at_picovolt-dot-com

 

[Gnekker]

Good day. I need an easy design for a frequency multiplier x100 to
drive a switched capacitor (SC) Bandpass-Filter.
The problem is (perhaps it isn´t a problem?) that the input frequency
will sweep between 500Hz up to 4,5kHz. I thought about using a PLL
with a divider by 100 between the VCO and the pase comparator. My
first steps with a LM565 PLL went wrong because I only know the PLL
basics and don´t know much about how to design a PLL ckt right.
What´s the point about free running frequency of the VCO? Do I have to
set it so a special frequency that the ckt will work fine? Are there
other possibilities to multiply a frequency x100? Can anyone help me?

Greets
ElCapitano

Using PIC and AD 9850 or AD 9851 you can produce sine wave with any
frequency from (almost) zero to ten's of megahertz, also with phase and
amplitude modulation.

 

[CFoley1064]

From: [email protected] (ElCapitano)

Date: 2/6/2004 1:47 AM Central Standard Time
Message-id: <[email protected]>

Good day. I need an easy design for a frequency multiplier x100 to
drive a switched capacitor (SC) Bandpass-Filter.
The problem is (perhaps it isn´t a problem?) that the input frequency
will sweep between 500Hz up to 4,5kHz. I thought about using a PLL
with a divider by 100 between the VCO and the pase comparator. My
first steps with a LM565 PLL went wrong because I only know the PLL
basics and don´t know much about how to design a PLL ckt right.
What´s the point about free running frequency of the VCO? Do I have to
set it so a special frequency that the ckt will work fine? Are there
other possibilities to multiply a frequency x100? Can anyone help me?

Greets
ElCapitano

Hi, El. For a newbie PLL design, you could do worse than look at the CD4046, a
CMOS PLL. The best one-stop shopping newbie intro to PLLs and the 4046 in
particular is in Don Lancaster's CMOS Cookbook, available through libraries or
at his website:

http://www.tinaja.com/

There's enough information there for you to work out a passable 4046 circuit
that will do what you need. Can't actually recommend values without knowing
more about your circuit requirements, but you should try it yourself. With the
datasheet and the CMOS Cookbook, you won't have any problems.

Good luck
Chris

 

[Jan Panteltje]

Good day. I need an easy design for a frequency multiplier x100 to
drive a switched capacitor (SC) Bandpass-Filter.
The problem is (perhaps it isn´t a problem?) that the input frequency
will sweep between 500Hz up to 4,5kHz. I thought about using a PLL
with a divider by 100 between the VCO and the pase comparator. My
first steps with a LM565 PLL went wrong because I only know the PLL
basics and don´t know much about how to design a PLL ckt right.
What´s the point about free running frequency of the VCO? Do I have to
set it so a special frequency that the ckt will work fine? Are there
other possibilities to multiply a frequency x100? Can anyone help me?

Greets
ElCapitano

Seems to me a 4046 followed by a divide by 100 stage, with the one
phase comparator (the one with the flip flops), would lock
(you need to pay attention to the pole loop filter).
450 kHz is way within its spec.

 

[mike]

Good day. I need an easy design for a frequency multiplier x100 to
drive a switched capacitor (SC) Bandpass-Filter.
The problem is (perhaps it isn´t a problem?) that the input frequency
will sweep between 500Hz up to 4,5kHz. I thought about using a PLL
with a divider by 100 between the VCO and the pase comparator. My
first steps with a LM565 PLL went wrong because I only know the PLL
basics and don´t know much about how to design a PLL ckt right.
What´s the point about free running frequency of the VCO? Do I have to
set it so a special frequency that the ckt will work fine? Are there
other possibilities to multiply a frequency x100? Can anyone help me?

Greets
ElCapitano

How fast does the input sweep?
What happens to the SC filter response when the clock frequency change
lags the frequency change of the input?
Even if it didn't lag, what's the response of a SC filter when
the clock frequency is changing?
You may have significant problems with the loop filter on the PLL.
Depending on the above answers, DDS *may* be a better option.
Something to think about.
mike

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[Al Clark]

On a sunny day (5 Feb 2004 23:47:50 -0800) it happened Chr- [email protected]
(ElCapitano) wrote in <91425d79.0402052347.7d1d1de5 @posting.google.com>:
Seems to me a 4046 followed by a divide by 100 stage, with the one
phase comparator (the one with the flip flops), would lock
(you need to pay attention to the pole loop filter).
450 kHz is way within its spec.

One more thing to consider with the 74HC4046:

The VCO differ with from manufacturerto manufacturer. I used this part in
the late 1980s and we had to specify specific manufacturers for the
circuit to work correctly with the values we selected.

I don't know the situation with the original 4046.

 

[Al Clark]

How fast does the input sweep?
What happens to the SC filter response when the clock frequency change
lags the frequency change of the input?
Even if it didn't lag, what's the response of a SC filter when
the clock frequency is changing?
You may have significant problems with the loop filter on the PLL.
Depending on the above answers, DDS *may* be a better option.
Something to think about.
mike

One more thought:

Have you considered a DSP for the filtering? Its very easy to produce
very good filters for this frequency range.

 

[Rene Tschaggelar]

One more thought:

Have you considered a DSP for the filtering? Its very easy to produce
very good filters for this frequency range.

Not if the filter is the input filter of a lock-in amplifier
and the signal is still -100dB down in the noise.

Rene

 

[ElCapitano]

Not if the filter is the input filter of a lock-in amplifier
and the signal is still -100dB down in the noise.

Rene

Thanks so far.

DSP? I´ve actually no experience in DSP circuits. Is there a device
which I can use for my intention (fx100) without programming it?

Greets
ElC.

PS: The frequency will sweep quite fast. But later the frequency will
stay in one one operating point so it would be nice if only the pll
won´t loose the right frequency. I don´t care so much about the
filters answer.

 

[Rene Tschaggelar]

DSP? I´ve actually no experience in DSP circuits. Is there a device
which I can use for my intention (fx100) without programming it?

PS: The frequency will sweep quite fast. But later the frequency will
stay in one one operating point so it would be nice if only the pll
won´t loose the right frequency. I don´t care so much about the
filters answer.

The suggestion was to take a DSP for the filtering. Because a DSP
can change the filtercoefficient on the fly, it would make it
possible to make it sweep in software. My concern was the dynamic
range of a digital system is the bit resolution of the DAC.

You're not doing synchroneous detection, lock-in or such ?

A PLL should keep the frequency nicely when the loopfilter is set
properly.

Rene

 

[Al Clark]

frequenc there m chang


The suggestion was to take a DSP for the filtering. Because a DSP
can change the filtercoefficient on the fly, it would make it
possible to make it sweep in software. My concern was the dynamic
range of a digital system is the bit resolution of the DAC.

You're not doing synchroneous detection, lock-in or such ?

A PLL should keep the frequency nicely when the loopfilter is set
properly.

Rene

There are many possible approaches to this problem. I am not sure which
approach would be the best (DSP versus analog PLL) and I am comfortable
in both worlds.

I assume that the reason for multiplying a reference frequency by 100 is
to allow you to use a switched C bandpass filter. You can multiply by a
much smaller N and do the same thing with a DSP filter. In this case, you
are allowing the sample rate of an ADC to vary. You don't need to change
coefficients in the DSP bandpass filter. The bandwidth of your filter
must not be too narrow in all cases. The faster you sweep, the wider the
bandwidth. The basic rule is that BT >= 1 (bandwidth x time). One DSP
advantage is that you could easily change the bandwidth of the filter
after you lock in the signal.

If you are comparing a switched C implemenation to a DSP, I don't think
dynamic range of the ADCs will be worst than the noise floor of the
switched C filter.

Tracking filters can be tricky and I know I have not addressed all the
details of your problem. My main point is that a DSP implementation is
really not all that different from a more analog approach.

I don't know of an of-the-shelf DSP solution.