Feedback resistor in CMOS Xtal oscillator.

[pimpom]

I'm experimenting with a 32.768kHz oscillator using a watch
crystal (no specs) and a CMOS inverter. The current limiting
resistor is 330k and the caps are both 15pF. It oscillates with
4.7-10Meg feedback resistor but not with 3.3M. I increased the Rf
in steps from 3.3M and it reluctantly starts up with 3.8M, taking
about 2 seconds to build up to full amplitude. Do you think 4.7M
will be enough to ensure oscillation with different samples of
the same type of crystal and under different environmental
conditions? The power supply is regulated.

(I have both practical considerations and an academic interest
for wanting to know if 4.7M is enough).

 

[pimpom]

Like any other shunt feedback circuit, too low a "feedback"
resistor
make the input impedance too low, make RF 10-20Meg like the
book says
and it'll be fine.

Larkin wouldn't know how to evaluate a crystal oscillator if
you gave
him a full-term course in the subject... I suspect too much
spanking
at Tulane Kindergarten

Thanks for the replies, both of you. ATM I have nothing higher
than 6.8Meg in stock, so I guess I'll just have to use two or
more in series.

 

[pimpom]

Quite a while ago, i posted a "semi-universal oscillator"
which
worked for "standard" crystals that take a "normal" drive, and
"tuning
fork" crystals that demand a rather low drive (level).
As i vaguely remember it, the input-to-output resistor for
the CMOS
gate was rather high - maybe 10Megs and i did not try to fiddle
with
that, thinking that substantially lower values would make for
excessive load on the crystal, creating a multiplicity of
un-intended
consequences (lower Q, frequency shift for starters).
I would say to use 10Megs and not look back.

OK. 10Meg it is (2x4.7M). The 6.8Ms I have are big - legacies
from vacuum tube days, and I wouldn't want to squeeze them in
unless I have to.

 

[Arie de Muynck]

Quite a while ago, i posted a "semi-universal oscillator" which worked
for "standard" crystals that take a "normal" drive, and "tuning fork"
crystals that demand a rather low drive (level).
As i vaguely remember it, the input-to-output resistor for the CMOS gate
was rather high - maybe 10Megs and i did not try to fiddle with that,
thinking that substantially lower values would make for excessive load on
the crystal, creating a multiplicity of un-intended consequences (lower Q,
frequency shift for starters).
I would say to use 10Megs and not look back.

Or, if the OP has only 1..2M resistors, use two in series and put a 1nF cap
from the connection to GND.

Arie