Examples of Boolean minimization

[cahlucas]

Hello everyone,
In connection with the development of a program for Boolean minimization, think e.g. to Quine-McCluskey, I need examples and their correct solution so that I can check my program for correct operation. The number of variables may not exceed 20, and preferably between 4 and 10. The examples may be presented in this form (see the truth table below): X {A, B, C, D} = Σ {2,4,5,6,9,10,13,14}, with the solution: CD'+A'BC'+AC'D (C AND (NOT D) OR (NOT A) AND B AND (NOT C) OR A AND (NOT C) AND D). I would like to receive a response from you. Kind regards, Karel.

 i  A B C D  X
 0  0 0 0 0  0
 1  0 0 0 1  0
 2  0 0 1 0  1
 3  0 0 1 1  0
 4  0 1 0 0  1
 5  0 1 0 1  1
 6  0 1 1 0  1
 7  0 1 1 1  0
 8  1 0 0 0  0
 9  1 0 0 1  1
10  1 0 1 0  1
11  1 0 1 1  0
12  1 1 0 0  0
13  1 1 0 1  1
14  1 1 1 0  1
15  1 1 1 1  0

 

[TCSC47]

Does anybody use Boolian Algebra nowadays?

 

[Harald Kapp]

Yes.

 

[TCSC47]

For work purposes or just an academic exercise? I really meant Boolian minimisation though. I remember using it once back in the 70's but logic circuitry was usually simple enough to be able to see the minimal use of gates without much problem.

I have to admit, I haven't been designing with logic circuitry for a number of years now and had assumed that any complicated logic circuitry was taken care of with microcontrollers. However, I am willing to be corrected.

Though of course there are the designers of the microcontrollers themselves who I think would find it useful, but how many of them are there?

 

[TCSC47]

Just to be quite clear, -- of course Boolian algebra will still be used. I was not thinking clearly. I meant Karnaugh maps which I have used in anger at the most only a couple of times. Just seemed like another of those academic exercises that you have to know for your terminal exam.

 

[Harald Kapp]

Maybe not explicitly, but implicitly: yes. Hidden within the tool used to generate logic for e.g. CPLDs, FPGAs...
Optimization today is probably not that relevant as it used to be as highly integrated chips with an abundance of logic gate are available so one can in many cases afford to forego optimization but implement the logic straight ahead.
Still, knowing how to optimize your logic is imho not a purely academic exercise: It may help you get the last bit of logic into your already crowded programmable component.

 

[Harald Kapp]

I need examples and their correct solution

There is often more than one correct solution.
Look up datasheets of logic chips like multiplexers, adders etc. These usually have the respective truth tables printed.

 

[cahlucas]

The program I am making will help me when I work with (simple) digital gate IC's. So no CPLD's, FPGA's and so on. All I need are samples, complete with correct answers, so that I can check my program for correct operation. Sincerely, Karel.