Eagle PCB: help with DRC errors

[Sumit Gupta]

Hi

I am using Eagle PCB to design a Xilinx fpga board. I used the XILINX
library provided on the cadsoft site and added the package TQ144 to my
board design. When I run DRC on this package it complains about
clearence between pads. Basically my requirement is that the clearence
should be more than 7mil. And as fas as I can see by putting the
package on a grid, it is more than 7 mil. Then why is DRC complaining
??

Sumit

 

[Chaos Master]

Sumit Gupta engraved with a +2 athame:

Hi

I am using Eagle PCB to design a Xilinx fpga board. I used the XILINX
library provided on the cadsoft site and added the package TQ144 to my
board design. When I run DRC on this package it complains about
clearence between pads. Basically my requirement is that the clearence
should be more than 7mil. And as fas as I can see by putting the
package on a grid, it is more than 7 mil. Then why is DRC complaining
??

I'd suggest you to adjust the DRC check parameters. I don't have Eagle installed
here, so I can't help you too much.

 

[Hal Murray]

I am using Eagle PCB to design a Xilinx fpga board. I used the XILINX

library provided on the cadsoft site and added the package TQ144 to my
board design. When I run DRC on this package it complains about
clearence between pads. Basically my requirement is that the clearence
should be more than 7mil. And as fas as I can see by putting the
package on a grid, it is more than 7 mil. Then why is DRC complaining

Is it complaining about every adjacent pair of pins being too
close, or just the places where you routed signals to a pin?

If it's complaining about every pair of pins, then your package
doesn't agree with your design rules. (at least as you currently
have things setup) If your package is what I think it is, the pads
are on 0.65 mm (25.6 mils) pitch. If the pads are 18 mils, then
there is 7 mils between pads. That should fit. If the pads are
19 mils, it won't fit.

If you did the routing on an inch grid and your wires are 7 mils,
they probably don't line up cleanly. They will jog from the center
of the pad (metric grid) slightly over to the inch grid used for
routing, then run out to the edge of the row of pads. That run out
is probably too close to the next pad. If this is your problem,
I'd suggest routing on a metric grid.

 

[Uwe Bonnes]

: Hi

: I am using Eagle PCB to design a Xilinx fpga board. I used the XILINX
: library provided on the cadsoft site and added the package TQ144 to my
: board design. When I run DRC on this package it complains about
: clearence between pads. Basically my requirement is that the clearence
: should be more than 7mil. And as fas as I can see by putting the
: package on a grid, it is more than 7 mil. Then why is DRC complaining
: ??

Understand and adjust the DRC rules. Fabricate the PCB according to the
these rules.

Bye