Do I need some sort of delay between two latch circuits?

[laylow]

I have two NOR latch circuits side by side.
The first NOR latch is set to Q=1
The second NOR latch is set to Q=0
A signal is sent simultaniously to reset the first latch and set the
second latch.
The outputs of both latches are sent to an AND latch circuit.
My intention is for the first NOR latch to reset before the second NOR
latch sets.

Will there be enough delay between the reset and set to prevent the
AND latch from setting?
If not, what is the easiest way to add sufficient delay to the second
NOR latches output?
Could I just use a slightly longer trace to the second latch?

I'm trying to keep the circuit as simple as possible so I would prefer
to not have to add some sort of delay circuit. If I do have to add a
circuit, could it be something simple that just uses some sort of
capacitor/resistor combination?

Thanks All,

Laylow

No email please, the account no longer exists.

 

[Rich Grise]

I have two NOR latch circuits side by side.
The first NOR latch is set to Q=1
The second NOR latch is set to Q=0
A signal is sent simultaniously to reset the first latch and set the
second latch.
The outputs of both latches are sent to an AND latch circuit.
My intention is for the first NOR latch to reset before the second NOR
latch sets.

Will there be enough delay between the reset and set to prevent the
AND latch from setting?
If not, what is the easiest way to add sufficient delay to the second
NOR latches output?
Could I just use a slightly longer trace to the second latch?

I'm trying to keep the circuit as simple as possible so I would prefer
to not have to add some sort of delay circuit. If I do have to add a
circuit, could it be something simple that just uses some sort of
capacitor/resistor combination?

The textbook should have all of the information you need to solve this,
albeit you might have to crib someone else's lecture notes.

Failing that, you could slap one together on a piece of perfboard,
get a scope, and see what happens.

Good Luck!
Rich

 

[Bill Sloman]

I have two NOR latch circuits side by side.
The first NOR latch is set to Q=1
The second NOR latch is set to Q=0
A signal is sent simultaniously to reset the first latch and set the
second latch.
The outputs of both latches are sent to an AND latch circuit.
My intention is for the first NOR latch to reset before the second NOR
latch sets.

Will there be enough delay between the reset and set to prevent the
AND latch from setting?
If not, what is the easiest way to add sufficient delay to the second
NOR latches output?
Could I just use a slightly longer trace to the second latch?

I'm trying to keep the circuit as simple as possible so I would prefer
to not have to add some sort of delay circuit. If I do have to add a
circuit, could it be something simple that just uses some sort of
capacitor/resistor combination?

You have to specify what sort of logic you are using, and what supply
voltage.

The information you need is buried in the data sheets for the devices that
you are actually using - the data sheets specify the range of propagation
delays you are likely to see, and the set-up times and hold times that you
will have to conform to if you want to be sure that the latches behave as
intended.

Even the fastest logic commercially available - ECLinPS - has propagation
delays, set-up times and hold times that aren't much less than a nanosecond,
which is about 20cm (eight inches) of propagation delay along a typical
printed circuit board, so using a longer trace is unlikely to be a practical
solution.

Resistor/capacitor lumped delays can work, but the large tolerances on the
logic threshold levels can make for very large tolerances (up to 10:1 in
some pathological cases) in the delay that you actually get.

I've used lumped constant delay lines, but this tends to be a bulky and
expensive solution. In clocked systems, you usually organise things so that
successive events happen on successive clock edges.

 

[MooseFET]

I have two NOR latch circuits side by side.
The first NOR latch is set to Q=1
The second NOR latch is set to Q=0
A signal is sent simultaniously to reset the first latch and set the
second latch.
The outputs of both latches are sent to an AND latch circuit.
My intention is for the first NOR latch to reset before the second NOR
latch sets.

Will there be enough delay between the reset and set to prevent the
AND latch from setting?
If not, what is the easiest way to add sufficient delay to the second
NOR latches output?
Could I just use a slightly longer trace to the second latch?

I'm trying to keep the circuit as simple as possible so I would prefer
to not have to add some sort of delay circuit. If I do have to add a
circuit, could it be something simple that just uses some sort of
capacitor/resistor combination?

Yes, a simple 1 Meg resistor feeding a 10 Farad capacitor will
certainly delay the signal enough if you are using any of the CMOS
technologies.

 

[laylow]

Unfortunately, I don't have a text book. I meant to get one once but
never did. I'm an amateur and by the time I get around to asking a
question in a group my brain is fairly mushy.

I was planning to use 74HC chips which I believe are CMOS circuits.
Are the 7400's TTL? Any reason why I might want to use the 7400's
instead of the 74HC's? The latches would be made by crossing the
outputs of two NOR gates with their inputs. The supply voltage is
5VDC.

It's good to know that the data I need should be buried in the data
sheets. I just hope that I can find it, recognize it, and understand
it.

So I guess I can look up the 74HC02's and hope that resetting is
faster than setting. If that fails, I can wait for my parts to come
in and see if the resistor/capacitor delay works for me. And if that
doesn't work then I guess it's time to learn about clocked systems.

Well, I'll read everything I can but believe me, I don't mind being
spoon-fed either.

Thanks Group!
Laylow

 

[laylow]

Unfortunately, I don't have a text book. I meant to get one once but
never did. I'm an amateur and by the time I get around to asking a
question in a group my brain is fairly mushy.

I was planning to use 74HC chips which I believe are CMOS circuits.
Are the 7400's TTL? Any reason why I might want to use the 7400's
instead of the 74HC's? The latches would be made by crossing the
outputs of two NOR gates with their inputs. The supply voltage is
5VDC.

It's good to know that the data I need should be buried in the data
sheets. I just hope that I can find it, recognize it, and understand
it.

So I guess I can look up the 74HC02's and hope that resetting is
faster than setting. If that fails, I can wait for my parts to come
in and see if the resistor/capacitor delay works for me. And if that
doesn't work then I guess it's time to learn about clocked systems.

Well, I'll read everything I can but believe me, I don't mind being
spoon-fed either.

Thanks Group!
Laylow

Sorry for being so redundant but I think I have a better idea of what
my question is now. Looking at the data sheet I can see that the
propagation delay for each gate is around 23ns. Resetting a latch
only requires the signal to pass through one gate while setting the
other latch requires the signal to pass through two gates. So I think
that means both latches will output low for about 23ns before the
second latch goes high. Is that enough to reliably prevent the AND
gate from going high? It's the reliable part that I'm concerned
about.

Thanks again,
Laylow

 

[neon]

if you do maping of the states you will get forbiden states no matter which gates you use.

 

[MooseFET]

Unfortunately, I don't have a text book.

Go buy "The Art Of Electronics".

I meant to get one once but

never did. I'm an amateur and by the time I get around to asking a
question in a group my brain is fairly mushy.

I was planning to use 74HC chips which I believe are CMOS circuits. Yes.
Are the 7400's TTL? Yes.
Any reason why I might want to use the 7400's
instead of the 74HC's?
Masochism.

The latches would be made by crossing the
outputs of two NOR gates with their inputs. The supply voltage is
5VDC.

It's good to know that the data I need should be buried in the data
sheets. I just hope that I can find it, recognize it, and understand
it.

So I guess I can look up the 74HC02's and hope that resetting is
faster than setting. If that fails, I can wait for my parts to come
in and see if the resistor/capacitor delay works for me. And if that
doesn't work then I guess it's time to learn about clocked systems.

The HC parts have about equal delays.

 

[laylow]

Go buy "The Art Of Electronics".

Yeah, that's the one. Okay, should be here in 3-5 days. If all the
hype about this book is true, blinding light will radiate from my head
after reading it. I'll probably still be back here asking questions
though.

 

[Don Lancaster]

Unfortunately, I don't have a text book.
Thanks Group!
Laylow

If you've seen one textbook, you've seen them all.

There's rumored to be a CMOS cookbook out there somewhere.

--
Many thanks,

Don Lancaster voice phone: (928)428-4073
Synergetics 3860 West First Street Box 809 Thatcher, AZ 85552
rss: http://www.tinaja.com/whtnu.xml email: [email protected]

Please visit my GURU's LAIR web site at http://www.tinaja.com

 

[Rich Grise]

Yeah, that's the one. Okay, should be here in 3-5 days. If all the
hype about this book is true, blinding light will radiate from my head
after reading it. I'll probably still be back here asking questions
though.

It would also be very helpful to learn to quote context - on USENET, with
a real newsreader, we can only see one post at a time.

Anyway, now that the netiquette is out of the way, lemme see if I got this
straight:

You have Two R-S Latches, and One Clock. In the Default State, RSL1 is
set, and RSL2 is clear; I'm guessing you've got RSL1Q and RSL2Q ANDed
together; and when the clock comes in, you want to guarantee that RSL1
will reset BEFORE RSL2 sets, so that there's no output from the AND.

Is that fairly close?

If so, just take two spare inverters from an HC04 and delay RSL2's "set"
signal.

But, why are you doing this?

Thanks!
Rich

 

[Rich Grise]

If you've seen one textbook, you've seen them all.

There's rumored to be a CMOS cookbook out there somewhere.

Howcome HCMOS is limited to +4.95V < Vcc < +5.05V? Has anybody
toyed with the idea of CMOS that has robust outputs but can run
from a higher Vcc? Or is the thrust these days to lower and lower
Vcc's?

Thanks,
Rich

 

[laylow]

It would also be very helpful to learn to quote context - on USENET, with
a real newsreader, we can only see one post at a time.

Anyway, now that the netiquette is out of the way, lemme see if I got this
straight:

You have Two R-S Latches, and One Clock. In the Default State, RSL1 is
set, and RSL2 is clear; I'm guessing you've got RSL1Q and RSL2Q ANDed
together; and when the clock comes in, you want to guarantee that RSL1
will reset BEFORE RSL2 sets, so that there's no output from the AND.

Is that fairly close?

Yes, except I was trying to stay away from using a clock. I can see
now that trying to build a logic circuit without a clock would be
extremely limiting. I also need to add a couple of triggers later so
I have to have the clock anyway.

If so, just take two spare inverters from an HC04 and delay RSL2's "set"
signal.

So just run the signal through two inverters in series? Does that
give me about 12 ns of propagation delay? Is propagation delay close
to actual signal delay?

But, why are you doing this?

I have two transducers and I want to be sure that they are firing in
order. If the order is reversed then I need an alarm to come on.
Transducer 1 sends a signal to RSL1's set and RSL2's reset.
Transducer 2 sends a signal to RSL1's reset and RSL2's set. Beyond
that, the answer starts to get a little existential.

Thanks!
Rich

Am I better off with 74HCs or 4000s? I thought I had a reason for
going with 74HCs but now I don't know. Speed is not an issue and
neither is power. Is one more complicated to work with than the
other?

Thanks,
Laylow

 

[John Fields]

I have two NOR latch circuits side by side.
The first NOR latch is set to Q=1
The second NOR latch is set to Q=0
A signal is sent simultaniously to reset the first latch and set the
second latch.
The outputs of both latches are sent to an AND latch circuit.
My intention is for the first NOR latch to reset before the second NOR
latch sets.

Will there be enough delay between the reset and set to prevent the
AND latch from setting?

---
Probably not. As others have suggested, consult the data sheets for
propagation delays, setup and hold times, etc.
---

If not, what is the easiest way to add sufficient delay to the second
NOR latches output?
Could I just use a slightly longer trace to the second latch?

---
1ns ~ 12" with a propagation velocity close to C, so that's not
really a viable strategy if what you mean by "slightly longer"
translates to a couple of inches of trace.
---

I'm trying to keep the circuit as simple as possible so I would prefer
to not have to add some sort of delay circuit. If I do have to add a
circuit, could it be something simple that just uses some sort of
capacitor/resistor combination?

---
Yup.

View in Courier:


+-----+
INIT>---------+--|S Q|------A +-----+
| | | AND Y--|S Q|-->OUT
SW>-------+---|--|R | +---B | |
| | +-----+ | +--|R |
[R] | | | +-----+
| | +-----+ | |
+---|--|S Q|--+ |
| | | | |
[C] +--|R | |
| | +-----+ |
GND>------+ +------------------+

The premise is that INIT will have a width long en ought to
establish the initial conditions and, once it decays, SW will be the
signal sent "simultaneously" to both latches.

However, because of the time constant of RC, the topmost latch will
reset before the bottom latch sets, ensuring that 'A' of the AND
will go low before 'B' goes high, also ensuring that 'Y' will stay
low during the transfer.

Is that what you want?

 

[Fred Bloggs]

I have two transducers and I want to be sure that they are firing in
order. If the order is reversed then I need an alarm to come on.
Transducer 1 sends a signal to RSL1's set and RSL2's reset.
Transducer 2 sends a signal to RSL1's reset and RSL2's set. Beyond
that, the answer starts to get a little existential.

Your description is too vague. If you can get more specific about the
transducers firing in order, and what they're firing, then we might be
able to suggest a "hazard free" implementation.

 

[MooseFET]

Howcome HCMOS is limited to +4.95V < Vcc < +5.05V? Has anybody
toyed with the idea of CMOS that has robust outputs but can run
from a higher Vcc? Or is the thrust these days to lower and lower
Vcc's?

It isn't limited like you suggest. It works from about 3V to about 6V

http://www.fairchildsemi.com/pf/MM/MM74HC04.html

To make a higher voltage part, the geometries have to get larger and
the on resistance of the FETs will increase. For a given cross
section, the on resistance runs as something like the square of the
breakdown voltage so going for a 3 times higher breakdown makes a 9
times increase in Rds(on).

If you make the cross section greater to lower the resistance, the
capacitances all increase.

I still want a PIC that can withstand some 35V however.

 

[laylow]

I have two NOR latch circuits side by side.
The first NOR latch is set to Q=1
The second NOR latch is set to Q=0
A signal is sent simultaniously to reset the first latch and set the
second latch.
The outputs of both latches are sent to an AND latch circuit.
My intention is for the first NOR latch to reset before the second NOR
latch sets.

Will there be enough delay between the reset and set to prevent the
AND latch from setting?

---
Probably not. As others have suggested, consult the data sheets for
propagation delays, setup and hold times, etc.
---

If not, what is the easiest way to add sufficient delay to the second
NOR latches output?
Could I just use a slightly longer trace to the second latch?

---
1ns ~ 12" with a propagation velocity close to C, so that's not
really a viable strategy if what you mean by "slightly longer"
translates to a couple of inches of trace.
---

I'm trying to keep the circuit as simple as possible so I would prefer
to not have to add some sort of delay circuit. If I do have to add a
circuit, could it be something simple that just uses some sort of
capacitor/resistor combination?

---
Yup.

View in Courier:

+-----+
INIT>---------+--|S Q|------A +-----+
| | | AND Y--|S Q|-->OUT
SW>-------+---|--|R | +---B | |
| | +-----+ | +--|R |
[R] | | | +-----+
| | +-----+ | |
+---|--|S Q|--+ |
| | | | |
[C] +--|R | |
| | +-----+ |
GND>------+ +------------------+

The premise is that INIT will have a width long en ought to
establish the initial conditions and, once it decays, SW will be the
signal sent "simultaneously" to both latches.

However, because of the time constant of RC, the topmost latch will
reset before the bottom latch sets, ensuring that 'A' of the AND
will go low before 'B' goes high, also ensuring that 'Y' will stay
low during the transfer.

Is that what you want?

Yes, that's it exactly. Thank you. I'm not exactly sure how to tell
how much delay is needed from the data sheets but it looks like I can
just pick a high enough RC time constant to be safe. I'm hoping that
when I get my AOE text and work book that I'll be more comfortable
with some of the more commonly used formulas. So far I have been
learning everything from sites like http://www.kpsec.freeuk.com/index.htm
and http://www.play-hookey.com/

LL

 

[laylow]

Your description is too vague. If you can get more specific about the
transducers firing in order, and what they're firing, then we might be
able to suggest a "hazard free" implementation.

Sorry. I am using two hall effect transducers to sense a magnet that
is mounted on a non-ferrous disc. It is important that the disc only
rotate in one direction. If the disc rotation reverses then an alarm
indicator needs to light up. The hall effect transducers pass a +5VDC
signal when the magnet passes them. If the disc itself were ferrous I
could just use a different kind of sensor entirely.

Thanks,
LL

 

[neon]

forbidden states means it may latch up in one state and renain latch up forever unless you or somthing reset it manualy. it doesn't know what to do. did the chicken comes before the egg type of question. look up keanouf i think is spelled like that maps. you may add an automatic reset at power up meaning force the gates into a set state.cross feeding gates have a forbiden state by logic consideration .

 

[Fred Bloggs]

Sorry. I am using two hall effect transducers to sense a magnet that
is mounted on a non-ferrous disc. It is important that the disc only
rotate in one direction. If the disc rotation reverses then an alarm
indicator needs to light up. The hall effect transducers pass a +5VDC
signal when the magnet passes them. If the disc itself were ferrous I
could just use a different kind of sensor entirely.

Thanks,
LL

Okay, now we know what you're trying to do. Run a search on "quadrature
rotary encoder" and see if that doesn't do much better...