Digital filter datapath using ROM

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I will be using VHDL\Verilog Code to simulate the function the
datapath proposed in this paper

"A New hardware Realization of Digital Filter"
By ABRAHAM PELED and BEDE LIU
IEEE Transaction on Acoustics,Speech and Signal Processing,DEC 1974

From Figure 2 in the paper,I could see that the shift registers used

are two 2 bit SIPO shift registers which would generate 5 bit address
for the ROM but the contents of ROM (phi ) is the 8 bit numbers and
the operation in adder (to find yn) also involves 8 bit numbers .So I
guess there are some contradiction since isn't the shift registers
supposed to be 8 bit too?

Please help me clarify