OK, here's my redesign. A lot of it is the same but I've changed how the preset and clear inputs of the 4510s are driven. IC6, the 4081 (or is it IC7, the 74LS08?) is no longer needed, and I've added a 4013 dual D flip-flop.
I'll only describe the changes here. On power-up, CR and RR produce a positive pulse to the SET input of IC6A so it starts up with its Q output high. This holds IC6B reset and holds the preset enable inputs (pin 1) of the counters active, forcing them to load 30 into their counters.
While IC6A is high, its Q-bar output is low; D5 keeps C1 discharged. This is an optional feature, to ensure that the oscillator starts counting after a fixed time relative to when the START button is pressed. If you don't want that feature, omit DS; in that case, the oscillator will run all the time, and depending on when you push the START button in relation to the oscillator cycle, the first down-count will occur between zero and one second after you press the button.
When you press SW1, the START button, a low level (from the D input) is clocked into IC6A so its Q output goes low. SW1 doesn't require debouncing because it doesn't matter if a low level is clocked into the flip-flop multiple times. When its Q output goes low, the counters are allowed to count downwards, which they do as originally designed; these counters have synchronous outputs and carry outputs which are designed for cascading. The count on the LED displays counts down from 30, and IC6B is no longer held reset.
Once the count reaches 00, on the next clock pulse, IC3's output pattern changes from 0000 to 1001, i.e. Q3 goes high. This sets IC6B whose Q output goes high, holding IC2 and IC3 reset. IC6B's Q-bar output on pin 12 can be used as an external signal to indicate when the counter has stopped; it is high during counting and goes low at the end of the count (after 00 has been displayed and the next clock pulse occurs).
The circuit remains in this state until the RESET button, SW2, is pressed. When this occurs, IC6A is set. This resets IC6B and removes the reset condition to IC2 and IC3, and asserts the preset condition, loading the count with 30 again and disabling the counter if DS is present. When the START button SW1 is pressed, counting starts again as described.
I've done a mental walk-through of this logic but I don't have a logic simulator I can use to test it, so there may be a fault in the logic. If you can simulate it before you build it, please do, and let me know if you find any problems.
As in your original schematic, the power pins and decoupling capacitors are not shown on the diagram, but are, of course, required.
