CMOS 555 triggering

[J. David]

Using a CMOS 555 (TLC555) at 5V , I wonder if tying both reset pin and
trigger pin together leads to a stable configuration as a monostable. The
reset/trigger pins being normally low, I would like to trigger the 555 just
by pulling them high and get a one single pulse.

So the question: will the 555 go out of reset state then acknowledge the
trigger because the trigger pin will also be low at that very moment? There
is a slight difference in levels between reset (around 1V) and trigger
(1.5V). But the rise time of the driving pulse being quite fast (in
nanoseconds), I can't figure out if the the internal circuitry will react
always the same way or unpredictably.

John

 

[Fred Bloggs]

Using a CMOS 555 (TLC555) at 5V , I wonder if tying both reset pin and

trigger pin together leads to a stable configuration as a monostable. The
reset/trigger pins being normally low, I would like to trigger the 555 just
by pulling them high and get a one single pulse.

So the question: will the 555 go out of reset state then acknowledge the
trigger because the trigger pin will also be low at that very moment? There
is a slight difference in levels between reset (around 1V) and trigger
(1.5V). But the rise time of the driving pulse being quite fast (in
nanoseconds), I can't figure out if the the internal circuitry will react
always the same way or unpredictably.

That would be a race condition with unpredictable results, my guess is
that the internal latch will remain reset because the trigger input will
not meet minimum pulsewidth requirements. It sounds like you want a high
going input to trigger a high going output, and this can't be done
without external components. Maybe you should forget the 555 and go with
a 74HC123.

 

[John B]

Using a CMOS 555 (TLC555) at 5V , I wonder if tying both reset pin
and trigger pin together leads to a stable configuration as a
monostable. The reset/trigger pins being normally low, I would like
to trigger the 555 just by pulling them high and get a one single
pulse.

So the question: will the 555 go out of reset state then acknowledge
the trigger because the trigger pin will also be low at that very
moment? There is a slight difference in levels between reset (around
1V) and trigger (1.5V). But the rise time of the driving pulse being
quite fast (in nanoseconds), I can't figure out if the the internal
circuitry will react always the same way or unpredictably.

John

Doesn't sound like a good idea. Try either tying the trigger pin low
and using the reset pin as your input or tying the reset pin high and
putting a BCR148 or similar digital transistor between your signal and
the trigger input.

 

[Fred Bloggs]

Using a CMOS 555 (TLC555) at 5V , I wonder if tying both reset pin and
trigger pin together leads to a stable configuration as a monostable. The
reset/trigger pins being normally low, I would like to trigger the 555 just
by pulling them high and get a one single pulse.

Since you're thinking about tying RST to the external trigger then this
must mean your 555 output pulsewidth is less than the external trigger
duration. A minimal monostable would then be something like below where
a ~150ns delay is introduced between the RST and TRIG inputs. When the
external trigger is applied, RST is lifted immediately and OUT goes high
because the 100p is discharged and TRIG is low. TRIG remains low for
about 150ns ensuring full propagation to the output. DIS turns off and
allows RT to charge CT. When CT charges to 2/3 x 5V, the 555 resets, OUT
goes low, DIS turns on and discharges CT. The external trigger holds
TRIG and RST high, and the 555 internal latch remains RST because TRIG
is high. When the external trigger is removed, RST is brought low
immediately, reinforcing the internal reset state, and TRIG goes low
about 400ns later. The action repeats upon application of next external
trigger. The 100 ohm in series with DIS is a current limiter. The output
pulse is truncated at any time by removal of the external trigger.
View in a fixed-width font such as Courier.

..
.. EXT TRIG ALWAYS LASTS LONGER THAN PW OUT
..
.. 5V
.. .------+----------------.
.. | | |
.. === [RT] |
.. 100P | |
.. | | |
.. | | |
.. .----+ | |
.. | | | |
.. | | | |
.. | | | |
.. | [3.9K] | |
.. | | | |
.. | | | +-------------+
.. EXT >--------+----------------|RST V+ |
.. TRIG | | | OUT|------>PW=1.1xRTxCT
.. | | | |
.. | +---------|THRESH |
.. | | | |
.. | +--[100]--|DIS |
.. | | | |
.. '---------------------|TRIG |
.. | | GND |
.. === +-------------+
.. CT |
.. | |
.. ---------------+----------------+------------------
..

 

[J. David]

Using a CMOS 555 (TLC555) at 5V , I wonder if tying both reset pin and
trigger pin together leads to a stable configuration as a monostable. The
reset/trigger pins being normally low, I would like to trigger the 555
just by pulling them high and get a one single pulse.

Since you're thinking about tying RST to the external trigger then this
must mean your 555 output pulsewidth is less than the external trigger
duration. A minimal monostable would then be something like below where a
~150ns delay is introduced between the RST and TRIG inputs. When the
external trigger is applied, RST is lifted immediately and OUT goes high
because the 100p is discharged and TRIG is low. TRIG remains low for about
150ns ensuring full propagation to the output. DIS turns off and allows RT
to charge CT. When CT charges to 2/3 x 5V, the 555 resets, OUT goes low,
DIS turns on and discharges CT. The external trigger holds TRIG and RST
high, and the 555 internal latch remains RST because TRIG is high. When
the external trigger is removed, RST is brought low immediately,
reinforcing the internal reset state, and TRIG goes low about 400ns later.
The action repeats upon application of next external trigger. The 100 ohm
in series with DIS is a current limiter. The output pulse is truncated at
any time by removal of the external trigger.
View in a fixed-width font such as Courier.

.
. EXT TRIG ALWAYS LASTS LONGER THAN PW OUT
.
. 5V
. .------+----------------.
. | | |
. === [RT] |
. 100P | |
. | | |
. | | |
. .----+ | |
. | | | |
. | | | |
. | | | |
. | [3.9K] | |
. | | | |
. | | | +-------------+
. EXT >--------+----------------|RST V+ |
. TRIG | | | OUT|------>PW=1.1xRTxCT
. | | | |
. | +---------|THRESH |
. | | | |
. | +--[100]--|DIS |
. | | | |
. '---------------------|TRIG |
. | | GND |
. === +-------------+
. CT |
. | |
. ---------------+----------------+------------------
.

Interesting circui to think about. Then may be this slight modification
could also work.
A high value resistor, say 100K, between EXT TRIGGER pulse and the trigger
pin. It would act as a pullup for the trigger pin. And pullup are never as
fast as direct driven input. The high value resistor and the input
capacitance of trigger pin (even if it is as small as 10pF) would be enough
to delay the trigger input by roughly 100K * 10pF / 2 = 500nS or so.
One less capacitor. Ok it sounds cheap but, this is the way I have alsways
designed electronic circuits.

.. 5V
.. +----------------.
.. | |
.. [RT] |
.. | |
.. | |
.. | |
.. | |
.. | |
.. | |
.. | |
.. | |
.. | |
.. | +-------------+
.. EXT >---+---------------------|RST V+ |
.. TRIG | | | OUT|------>PW=1.1xRTxCT
.. | | | |
.. [100K] +---------|THRESH |
.. | | | |
.. | +--[100]--|DIS |
.. | | | |
.. '---------------------|TRIG |
.. | | GND |
.. === +-------------+
.. CT |
.. | |
.. ---------------+----------------+------------------
..

 

[Fred Bloggs]

Using a CMOS 555 (TLC555) at 5V , I wonder if tying both reset pin and
trigger pin together leads to a stable configuration as a monostable. The
reset/trigger pins being normally low, I would like to trigger the 555
just by pulling them high and get a one single pulse.

Since you're thinking about tying RST to the external trigger then this
must mean your 555 output pulsewidth is less than the external trigger
duration. A minimal monostable would then be something like below where a
~150ns delay is introduced between the RST and TRIG inputs. When the
external trigger is applied, RST is lifted immediately and OUT goes high
because the 100p is discharged and TRIG is low. TRIG remains low for about
150ns ensuring full propagation to the output. DIS turns off and allows RT
to charge CT. When CT charges to 2/3 x 5V, the 555 resets, OUT goes low,
DIS turns on and discharges CT. The external trigger holds TRIG and RST
high, and the 555 internal latch remains RST because TRIG is high. When
the external trigger is removed, RST is brought low immediately,
reinforcing the internal reset state, and TRIG goes low about 400ns later.
The action repeats upon application of next external trigger. The 100 ohm
in series with DIS is a current limiter. The output pulse is truncated at
any time by removal of the external trigger.
View in a fixed-width font such as Courier.

.
. EXT TRIG ALWAYS LASTS LONGER THAN PW OUT
.
. 5V
. .------+----------------.
. | | |
. === [RT] |
. 100P | |
. | | |
. | | |
. .----+ | |
. | | | |
. | | | |
. | | | |
. | [3.9K] | |
. | | | |
. | | | +-------------+
. EXT >--------+----------------|RST V+ |
. TRIG | | | OUT|------>PW=1.1xRTxCT
. | | | |
. | +---------|THRESH |
. | | | |
. | +--[100]--|DIS |
. | | | |
. '---------------------|TRIG |
. | | GND |
. === +-------------+
. CT |
. | |
. ---------------+----------------+------------------
.

Interesting circui to think about. Then may be this slight modification
could also work.
A high value resistor, say 100K, between EXT TRIGGER pulse and the trigger
pin. It would act as a pullup for the trigger pin. And pullup are never as
fast as direct driven input. The high value resistor and the input
capacitance of trigger pin (even if it is as small as 10pF) would be enough
to delay the trigger input by roughly 100K * 10pF / 2 = 500nS or so.
One less capacitor. Ok it sounds cheap but, this is the way I have alsways
designed electronic circuits.

. 5V
. +----------------.
. | |
. [RT] |
. | |
. | |
. | |
. | |
. | |
. | |
. | |
. | |
. | |
. | +-------------+
. EXT >---+---------------------|RST V+ |
. TRIG | | | OUT|------>PW=1.1xRTxCT
. | | | |
. [100K] +---------|THRESH |
. | | | |
. | +--[100]--|DIS |
. | | | |
. '---------------------|TRIG |
. | | GND |
. === +-------------+
. CT |
. | |
. ---------------+----------------+------------------
.

That looks very good and should work well. Looking at the datasheet,
they show an R-/R-S latch where TRIG drives S through a comparator and
RST drives /R directly. With your triggering, the /R is long inactive
before the TRIG high starts to deactivate S after the comparator delay,
so if your rise time is very fast, like <25ns, it should put the latch
in the SET state, and the output should go high. That 100K of yours will
help that situation even more. But I wouldn't try it without the 100K
since there's an unknown minimum TRIG application time in there
somewhere, of unspecified character.

 

[J. David]

Interesting circui to think about. Then may be this slight modification
could also work.
A high value resistor, say 100K, between EXT TRIGGER pulse and the
trigger pin. It would act as a pullup for the trigger pin. And pullup are
never as fast as direct driven input. The high value resistor and the
input capacitance of trigger pin (even if it is as small as 10pF) would
be enough to delay the trigger input by roughly 100K * 10pF / 2 = 500nS
or so.
One less capacitor. Ok it sounds cheap but, this is the way I have
alsways designed electronic circuits.

. 5V
. +----------------.
. | |
. [RT] |
. | |
. | |
. | |
. | |
. | |
. | |
. | |
. | |
. | |
. | +-------------+
. EXT >---+---------------------|RST V+ |
. TRIG | | | OUT|------>PW=1.1xRTxCT
. | | | |
. [100K] +---------|THRESH |
. | | | |
. | +--[100]--|DIS |
. | | | |
. '---------------------|TRIG |
. | | GND |
. === +-------------+
. CT |
. | |
. ---------------+----------------+------------------
.

That looks very good and should work well. Looking at the datasheet, they
show an R-/R-S latch where TRIG drives S through a comparator and RST
drives /R directly. With your triggering, the /R is long inactive before
the TRIG high starts to deactivate S after the comparator delay, so if
your rise time is very fast, like <25ns, it should put the latch in the
SET state, and the output should go high. That 100K of yours will help
that situation even more. But I wouldn't try it without the 100K since
there's an unknown minimum TRIG application time in there somewhere, of
unspecified character.

Thanks for your insight.
For your curiosity, this circuit is intended to discriminate between a short
60us pulse and a longer 120uS pulse and record the result. PW would be set
in between, let's say 90uS.
When the pulse ends, its falling edge is sent to an active-low clock input
of a D flip-flop. The D input of the flip-flop is connected to the output of
the 555. The flip-flop would (should...) record a 1 if the pulse is shorter,
a 0 if longer.