clock distribution

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Now i am designing the clock distribution net work of a digitizer
system, The digitizer we design have two channels, each channel can
accquire data at 200Ms/s, and now we need that the two channels should
be synchronized no more that 100ps.So can any one who has done this
kind of design before give me some advice or tell me some ics that fit
this design?
Welcome new methods too. thanks