Chaining HCF4094 Shift Registers

[Mark Herhold]

I've got HCF4094 shift registers that have (poorly named IMO) outputs names Qs and Q's . I don't understand how to chain multiple registers together. My guess is that Qs maps to the strobe and Q's maps to data, but I honestly don't know how to figure it out. I find it irritating that the datasheet doesn't prescribe an out-of the box solution given that is the purpose of Qs and Q's...

Any help would be appreciated.

Datasheet:
http://www.st.com/web/en/resource/technical/document/datasheet/CD00000399.pdf

 

[Harald Kapp]

The clue is in figure 5 on page 6:

• Qs changes with the rising edge of clok.
• Q's is phase-shifted by 1/2 clock, thus changes with the falling edge of clock.

When cascading the registers you have to ensure setup and hold times at the input of the second register, therefore use Q's. If you were to use Qs, the output of the first register and thus the input to the second register changes with the rising edge of clock. This is likely to violate the hold eime requirement for the input of the second register.

Figure 6 on page 10 shows how to cascade multiple 4094s.

 

[Mark Herhold]

Thank you Harald. What you said makes a lot of sense. I missed figure 5 multiple times it seems...

What do you think the intended application/use case around Qs?

 

[Herschel Peeler]

The clue is in figure 5 on page 6:

• Qs changes with the rising edge of clok.
• Q's is phase-shifted by 1/2 clock, thus changes with the falling edge of clock.

When cascading the registers you have to ensure setup and hold times at the input of the second register, therefore use Q's. If you were to use Qs, the output of the first register and thus the input to the second register changes with the rising edge of clock. This is likely to violate the hold eime requirement for the input of the second register.

Figure 6 on page 10 shows how to cascade multiple 4094s.

An example

 

[Harald Kapp]

What do you think the intended application/use case around Qs?

Anythingb that needs to be faster than Q's. E.g. if you need to perform some logic functions on the output of the shift register before latching the result into another register with the same clock. The logic function may give you enough delay to ensure setup and hold times to the second register, but you wouldn't want to lose 1/2 clock cycle using Q's.