C2 in Switching Buck Regulator

[steroidmicros]

There are the issues of capacitance and ESR when choosing C2 (Cout).

As far as I can tell, there is a C2 capacitance threshold, below which
the switcher becomes unstable.

As long as the minimum capacitance is met, then the key factor is ESR:
The lower the ESR, the lower the output ripple.

My question is this: Can one use 2 capacitors in parallel in place of
C2: One electrolytic cap (high C, high ESR) to provide the required
capacitance for stability, and a second ceramic capacitor (low C, low
ESR) to reduce ripple?

How can one analyse such a circuit?

Thanks,

Bob Furber

 

[Genome]

| There are the issues of capacitance and ESR when choosing C2 (Cout).
|
| As far as I can tell, there is a C2 capacitance threshold, below which
| the switcher becomes unstable.
|
| As long as the minimum capacitance is met, then the key factor is ESR:
| The lower the ESR, the lower the output ripple.
|
| My question is this: Can one use 2 capacitors in parallel in place of
| C2: One electrolytic cap (high C, high ESR) to provide the required
| capacitance for stability, and a second ceramic capacitor (low C, low
| ESR) to reduce ripple?
|
| How can one analyse such a circuit?
|
| Thanks,
|
| Bob Furber

If you mentioned what sort of control scheme/IC you were using then you
might get more informed answers.

DNA

 

[Joerg]

Hi Bob,

Please mind the ripple current rating of the electrolytic as well. ESR
data is not really a good measure to determine which cap shares how much
of the total ripple current. What if the particular production batch of
electrolytics is much lower in ESR than the data sheet says? When the
current rating is exceeded a capacitor might become hot, hotter, more
hot and then....kapoof.

Mostly it is better to use similar capacitors in parallel and make sure
everyone of them runs within all their specs including allowed ripple
current.

Regards, Joerg

 

[Bob Wilson]

There are the issues of capacitance and ESR when choosing C2 (Cout).

As far as I can tell, there is a C2 capacitance threshold, below which
the switcher becomes unstable.

As long as the minimum capacitance is met, then the key factor is ESR:
The lower the ESR, the lower the output ripple.

My question is this: Can one use 2 capacitors in parallel in place of
C2: One electrolytic cap (high C, high ESR) to provide the required
capacitance for stability, and a second ceramic capacitor (low C, low
ESR) to reduce ripple?

How can one analyse such a circuit?

As someone else has already pointed out, without telling us what topology you
are considering, you can't get any meaningful answers to your question.

But in general, it is NOT as simple as you may think. For example, the output
cap's ESR, in series with its capacitance, results in a Zero at the frequency
where capacitive reactance equals ESR. This can be VERY useful. It is very
common practice in flybacks, for example, to select an output cap with a
specific capacitance and approximate ESR, so that this Zero occurs somewhat
before the loop gain falls through 0dB. This adds phase margin to improve
stability, while still allowing high DC and low frequency gain.

In the above instance, an "ideal" cap with zero ESR would result in a totally
unstable system.

Bob.

 

[colin]

There are the issues of capacitance and ESR when choosing C2 (Cout).

As far as I can tell, there is a C2 capacitance threshold, below which
the switcher becomes unstable.

As long as the minimum capacitance is met, then the key factor is ESR:
The lower the ESR, the lower the output ripple.

My question is this: Can one use 2 capacitors in parallel in place of
C2: One electrolytic cap (high C, high ESR) to provide the required
capacitance for stability, and a second ceramic capacitor (low C, low
ESR) to reduce ripple?

How can one analyse such a circuit?

to anaylsyse it simply, just work out the reactance of the capacitors at
specific frequencies (1/2piFC) and add on the ESR (wich is usualy dependant
on freq anyway)

youl then find that one capacitor dominates (the high value one) for low
frequencies and the other might dominate for high frequencies, but low esr
is relative, a large electrolytic or especialy tantalum that isnt considered
low esr might actualy have lower esr than some ceramic caps of much smaller
value anyway.

Colin. =^.^=

 

[steroidmicros]

As someone else has already pointed out, without telling us what topology you

are considering, you can't get any meaningful answers to your question.

Agrred. This is a simple buck circuit. That is: Vin -> switch -> L1 ->
Vout
and C1 between Vin and Gnd, D1 between Vsw and Gnd and C2 between Vout
and Gnd

The switch is actualy embedded in the switching regulator, which in
this case is a National Semi LM2675-5.0.

But in general, it is NOT as simple as you may think. For example, the output
cap's ESR, in series with its capacitance, results in a Zero at the requency
where capacitive reactance equals ESR. This can be VERY useful. It is very
common practice in flybacks, for example, to select an output cap with a
specific capacitance and approximate ESR, so that this Zero occurs somewhat
before the loop gain falls through 0dB. This adds phase margin to improve
stability, while still allowing high DC and low frequency gain.

Hmmmm... would this apply to a simple buck switcher as I described
above? No mention in the datasheets. Just choose a C2 with as high
capacitance and as low ESR as one can afford.

However, playing around with WebBench on National's website indicated
that, above a certain minimum value, C2's capacitance had very little
effect on anything. But, its ESR had a direct impact on output ripple.
Below the minimum capacitance, the LP2675 circuit's output oscillated
widely.

Hence my question about whether one can separate the 2 functions:
Stability (large cheap cap with high ESR) and Ripple (small cheap
ceramic with low ESR).

In the above instance, an "ideal" cap with zero ESR would result in a
totally unstable system.

Thanks,

Bob Furber

 

[Bob Wilson]

Hmmmm... would this apply to a simple buck switcher as I described
above? No mention in the datasheets. Just choose a C2 with as high
capacitance and as low ESR as one can afford.

Naturally there is no mention of this in datasheets, because this is not a
datasheet issue. It is an issue related to loop stability, which is
something that many of these "switchmode regulators for dummies" chips
don't bother much with.

Most of these type of chips show applications notes that have VERY
sluggish control/feedback networks because they have no idea what you are
using them for. So they play it safe and have high DC gain, and then
immediately roll the closed loop response off in a nice gentle
characteristic that gives lots of phase margin. The cost of this is lousy
transient response, because even at a few hertz, the closed loop response
is already rolling off rapidly.

Remember that buck regulator is INHERENTLY unstable unless at least one
Zero is added at an appropriate point. The Buck inductor combined with the
output cap automatically results in a 180 degree phase shift at higher
frequencies. Coupled with the additional 180 degrees that is inherent in a
negative feedback path, the result is a 360 degree phase shift. Not a good
thing!

One way or another, one must counteract at least ONE of the poles
resulting from the output LC, by inserting a Zero. The bottom line is that
the 2-Pole rolloff characteristic (with increasing frequency) MUST be
reduced so that, as the closed loop Bode plot approaches 0dB closed loop
gain, the 180 degree phase shift due to the output LC is reduced by at
least 45 degrees as the closed loop reponse passes through the 0dB point.

There are various ways to do this. One is to do it with a suitable network
in the error amplifier. Another is to take advantage of the Cap's ESR. But
either way, ESR must be considered. In the first method, all that is
needed is to ensure that ESR doesn't cause an unintended additional Zero
where you don't expect it.

For best transient response, and best ability to respond to line and load
changes, the ideal situation is to have high DC gain that extends out to
several hundred hertz. Then this is followed by a rapid 2-pole rolloff
that then pulls back to a one-pole characteristic just as the closed loop
gain approaches zero db. The sharper the initial rolloff characteristic,
the higher the frequency you can maintain high DC gain, before you have to
start the rolloff.

However, playing around with WebBench on National's website indicated
that, above a certain minimum value, C2's capacitance had very little
effect on anything. But, its ESR had a direct impact on output ripple.
Below the minimum capacitance, the LP2675 circuit's output oscillated
widely.

It has a direct impact on output ripple, because at high frequency, ESR is
generally much higher than the actual capacitive reactance.

Hence my question about whether one can separate the 2 functions:
Stability (large cheap cap with high ESR) and Ripple (small cheap
ceramic with low ESR).

A large cheap cap may have very low capacitive reactance, but the problem
is (as mentioned above) that you have a much larger resistive component
(the ESR) in series with the cap, making it act not much like a cap at
high frequency. At 100kHz, the ESR can be thought of as forming a voltage
divider with the inductive reactance of the inductor. Thus the actual
value of the capacitor is not really what influences the output ripple at
all.

Bob.

 

[Genome]

| > As someone else has already pointed out, without telling us what
topology you
| > are considering, you can't get any meaningful answers to your
question.
|
| Agreed. This is a simple buck circuit. That is: Vin -> switch -> L1 ->
| Vout and C1 between Vin and Gnd, D1 between Vsw and Gnd and C2
| between Vout and Gnd
|
| The switch is actualy embedded in the switching regulator, which in
| this case is a National Semi LM2675-5.0.
|
| > But in general, it is NOT as simple as you may think. For example,
| > the output cap's ESR, in series with its capacitance, results in a
| > Zero at the requency where capacitive reactance equals ESR.
| > This can be VERY useful. It is very common practice in flybacks, for
| > example, to select an output cap with a specific capacitance and
| > approximate ESR, so that this Zero occurs somewhat before the loop
gain
| > falls through 0dB. This adds phase margin to improve stability,
while still
| > allowing high DC and low frequency gain.
|
| Hmmmm... would this apply to a simple buck switcher as I described
| above? No mention in the datasheets. Just choose a C2 with as high
| capacitance and as low ESR as one can afford.
|
| However, playing around with WebBench on National's website indicated
| that, above a certain minimum value, C2's capacitance had very little
| effect on anything. But, its ESR had a direct impact on output ripple.
| Below the minimum capacitance, the LP2675 circuit's output oscillated
| widely.
|
| Hence my question about whether one can separate the 2 functions:
| Stability (large cheap cap with high ESR) and Ripple (small cheap
| ceramic with low ESR).
|
| > In the above instance, an "ideal" cap with zero ESR would result in
| > a totally unstable system.
|
| Thanks,
|
| Bob Furber

As Bob Wilson mentions in a later post there is precious little
information
given in the datasheet regarding loop stability considerations. Perhaps
this information might be found elsewhere but I would doubt it.

The most you can get is from the block diagram where there are two gm
stages with associated compensation components around them and an
indication of the ramp amplitude of the oscillator. Unfortunately there
is no information about the gain of these gm stages other than the
second is made proportional to the input supply. This is necessary
because gain is dependent on VIN and this provides a first order
compensation for the effect.

Without knowing the relative levels of these gains there's not much you
can do. You're given what you get and that's it. Perhaps an e-mail to
the manufacturer would get you some more solid information.

However you can get some idea about what could be going on from the
relative locations of the circuit poles and zeros.

The second gm stage has a DC pole due to the 10nF capacitor with a zero
set by the 15K resistor at about 1KHz. The feedback gain is first order
up to this frequency and then becomes zero order.

The first gm stage gain is flat up to the point where the 2K resistor
and 20mH inductor introduce a zero in the response at 15KHz. This zero
is cancelled by the 10K resistor at about 80KHz. I'd make the assumption
that it is this zero that is used to cancel one of the LC output filter
poles. Crossover frequency would be expected to lie between 15K and 80K

That means the LC section resonance must occur below, or not too far
above, 15KHz so I would assume that having used the nomograms to select
a value for LOUT the ones used to select an output capacitor, COUT, to
achieve something close to this. Obviously if COUT is set too low then
the resonace will occur at too high a frequency and the system is likely
to be ubstable.

In this case if the ESR zero frequency is below crossover then there is
unlikely to be a problem with general stability. However, if the ESR is
too large, you will probably suffer with subharmonic oscillation,
unequal pulse widths In a situation with zero or minimal ESR the system
should still be stable.

All of which is speculative rubbish without knowing more about what's in
the IC.

However, your suggestion of using two capacitors to achieve lower ripple
currents may well be valid.

Some more speculation.

I would suggest that you select the inductor on the basis of the
prescribed design procedure. Then select a COUT1 with a value which
places the filter resonance at 15KHz. Use a device whose ESR is equal to
the LC section impedance at resonance. Then pick a value for COUT2,
low/zero ESR, with a value that is 1/3 of COUT1. Place them in parallel.

The result should be a critically damped LC section which fits in with
the gm sections compensation method.

DNA

 

[Genome]

|
| However, your suggestion of using two capacitors to achieve lower
ripple
| currents may well be valid.
|
| Some more speculation.
|
| I would suggest that you select the inductor on the basis of the
| prescribed design procedure. Then select a COUT1 with a value which
| places the filter resonance at 15KHz. Use a device whose ESR is equal
to
| the LC section impedance at resonance. Then pick a value for COUT2,
| low/zero ESR, with a value that is 1/3 of COUT1. Place them in
parallel.
|
| The result should be a critically damped LC section which fits in with
| the gm sections compensation method.
|
| DNA
|
|

Ooops, that's wrong.

Select the inductor on the basis of the nomographs. Pick a low/zero ESR
capacitor which places the filter resonance at 15KHz. Add the larger
capacitor 3 times the smaller ones value in parallel and pick its ESR to
be the same as the resonant impedance at 15KHz.........

In the 5V 1A example.

L = 47uH

Gives 2u2, film or ceramic for low/zero ESR. Frez = 15KHz. Impedance at
resonance is 4R4, call it 4R7. Add a 6u8 film or ceramic low/zero ESR in
series with a 4R7 resistor in parallel with the original.

And that's probably wrong as well.....

DNA

 

[colin]

Naturally there is no mention of this in datasheets, because this is not a
datasheet issue. It is an issue related to loop stability, which is
something that many of these "switchmode regulators for dummies" chips
don't bother much with.

Most of these type of chips show applications notes that have VERY
sluggish control/feedback networks because they have no idea what you are
using them for. So they play it safe and have high DC gain, and then
immediately roll the closed loop response off in a nice gentle
characteristic that gives lots of phase margin. The cost of this is lousy
transient response, because even at a few hertz, the closed loop response
is already rolling off rapidly.

Remember that buck regulator is INHERENTLY unstable unless at least one
Zero is added at an appropriate point. The Buck inductor combined with the
output cap automatically results in a 180 degree phase shift at higher
frequencies. Coupled with the additional 180 degrees that is inherent in a
negative feedback path, the result is a 360 degree phase shift. Not a good
thing!

One way or another, one must counteract at least ONE of the poles
resulting from the output LC, by inserting a Zero. The bottom line is that
the 2-Pole rolloff characteristic (with increasing frequency) MUST be
reduced so that, as the closed loop Bode plot approaches 0dB closed loop
gain, the 180 degree phase shift due to the output LC is reduced by at
least 45 degrees as the closed loop reponse passes through the 0dB point.

There are various ways to do this. One is to do it with a suitable network
in the error amplifier. Another is to take advantage of the Cap's ESR. But
either way, ESR must be considered. In the first method, all that is
needed is to ensure that ESR doesn't cause an unintended additional Zero
where you don't expect it.

For best transient response, and best ability to respond to line and load
changes, the ideal situation is to have high DC gain that extends out to
several hundred hertz. Then this is followed by a rapid 2-pole rolloff
that then pulls back to a one-pole characteristic just as the closed loop
gain approaches zero db. The sharper the initial rolloff characteristic,
the higher the frequency you can maintain high DC gain, before you have to
start the rolloff.


It has a direct impact on output ripple, because at high frequency, ESR is
generally much higher than the actual capacitive reactance.


A large cheap cap may have very low capacitive reactance, but the problem
is (as mentioned above) that you have a much larger resistive component
(the ESR) in series with the cap, making it act not much like a cap at
high frequency. At 100kHz, the ESR can be thought of as forming a voltage
divider with the inductive reactance of the inductor. Thus the actual
value of the capacitor is not really what influences the output ripple at
all.

Bob.

ESR adds extra ripple voltage most easily calculable from using the ripple
current and ohms law. ie 2amp ripple and 50miliohom esr = 100mv ripple.
this would be in adition to the 20mv from a perfect 1000uf capacitor at
100khz wich has a reactance of about 10milliohms

normaly ripple current is determined almost entirley by the inductor of
course. (v=Ldi/dt)

actualy if you want to get ripple down using 2 cheap high esr capacitors,
you could just put a small choke between the 2 capacitors. low enough to not
have any much effect at loop feedback frequencies, but just enough to reduce
the ripple by a reasonable factor.

in fact you could always still take the feedback point from the first
capacitor. as its dc resistance shhould be almost negligable.

colin =^.^=

 

[Bob Wilson]

ESR adds extra ripple voltage most easily calculable from using the ripple
current and ohms law. ie 2amp ripple and 50miliohom esr = 100mv ripple.
this would be in adition to the 20mv from a perfect 1000uf capacitor at
100khz wich has a reactance of about 10milliohms

normaly ripple current is determined almost entirley by the inductor of
course. (v=Ldi/dt)

actualy if you want to get ripple down using 2 cheap high esr capacitors,
you could just put a small choke between the 2 capacitors. low enough to not
have any much effect at loop feedback frequencies, but just enough to reduce
the ripple by a reasonable factor.

in fact you could always still take the feedback point from the first
capacitor. as its dc resistance shhould be almost negligable.

Agreed. In fact, it is a pretty standard approach to take your feedback point
from before this additional LC. as you say, this will avoid any additional
effects caused by the poles of this pair.

Bob.

 

[steroidmicros]

As someone else has already pointed out, without telling us what topology you

are considering, you can't get any meaningful answers to your question.

Agrred. This is a simple buck circuit. That is: Vin -> switch -> L1 ->
Vout
and C1 between Vin and Gnd, D1 between Vsw and Gnd and C2 between Vout
and Gnd

The switch is actualy embedded in the switching regulator, which in
this case is a National Semi LM2675-5.0.

But in general, it is NOT as simple as you may think. For example, the output
cap's ESR, in series with its capacitance, results in a Zero at the requency
where capacitive reactance equals ESR. This can be VERY useful. It is very
common practice in flybacks, for example, to select an output cap with a
specific capacitance and approximate ESR, so that this Zero occurs somewhat
before the loop gain falls through 0dB. This adds phase margin to improve
stability, while still allowing high DC and low frequency gain.

Hmmmm... would this apply to a simple buck switcher as I described
above? No mention in the datasheets. Just choose a C2 with as high
capacitance and as low ESR as one can afford.

However, playing around with WebBench on National's website indicated
that, above a certain minimum value, C2's capacitance had very little
effect on anything. But, its ESR had a direct impact on output ripple.
Below the minimum capacitance, the LP2675 circuit's output oscillated
widely.

Hence my question about whether one can separate the 2 functions:
Stability (large cheap cap with high ESR) and Ripple (small cheap
ceramic with low ESR).

In the above instance, an "ideal" cap with zero ESR would result in a
totally unstable system.

Thanks,

Bob Furber

 

[steroidmicros]

Thanks to all who contributed to this thread. Regrettably much of it
was over my head. So, I did a little experimenting using a LM2675
swithing [buck] regulator (260KHz).

Standard conditions:
Vin = 24vdc wallwart
0.4vac <- Ripple
Vout = 5vdc
Rld = 5 ohms
Iout = 1 amp

Experiment 1
Cin = 4.7uF/50v Y5V ceramic. ESR unknown, but presumed low.
L = 47uH, 0.14 ohm, 1.5a
Cout = 100uF/10v std grade electrolytic. ESR unknown. Probably about 1
ohm.
Vout = 0.7vac <- Ripple

Experiment 2
Cin = 4.7uF/50v Y5V ceramic. ESR unknown, but presumed low.
L = 47uH, 0.14 ohm, 1.5a
Cout = 100uF/10v std grade electrolytic. ESR unknown. Probably about 1
ohm.
+ 4.7uF/10v Y5V ceramic. ESR unknown, but presumed low.
Vout = 0.15vac <- Ripple

Conclusion

A moderate ceramic cap in parralel with a high ESR, but otherwise
suitably sized cap, seems to reduce Vout ripple quite dramatically.

What we don't know is whether this ripple reducing cap affects
switcher stability, putting it closer to the "edge".

 

[Ole Moyer]

To help our customers understand feedback network theory, I wrote a program
in LabVIEW that allows the user to interactively change parameters while the
computer graphically displays the gain and phase response.

The program is ideal for illustrating the effects of large "crap caps" often
used to improve stability, and the potential pitfalls of low esr ceramic
capacitors.

The tool is free, and can be downloaded from:

http://www.onsemi.com/site/products/summary/0,4450,NCP5210,00.html#Software

The zip file contains a windows installer for the LabVIEW runtime engine,
and the executable files for the program.

The documentation (and a new version) is still being created, so don't look
too hard for it.

The tool is very useful for understanding the effects of different component
values on the loop response. It is ideal for students, and useful for design
engineers.

Using the program is simple, 1) select a component or value to be changed by
clicking on it 2) change the value by moving the slider or entering a value
in the display box 3) see the gain and phase response of the power stage,
compensator, or the entire loop. The output impendence over frequency is
also available.

The equations assume a linear average model, so switching effects and
voltage clipping are not considered.

I hope someone finds it useful

Ole Moyer
Apps Engineer
ON Semiconductor

 

[Rich Grise]

Thanks to all who contributed to this thread. Regrettably much of it
was over my head. So, I did a little experimenting using a LM2675
swithing [buck] regulator (260KHz).

It kinda looks like the
http://www.national.com/ds/LM/LM2825.pdf
will do it in one chip!

 

[Winfield Hill]

Rich Grise wrote...

Thanks to all who contributed to this thread. Regrettably much
of it was over my head. So, I did a little experimenting using
a LM2675 swithing [buck] regulator (260KHz).

It kinda looks like the http://www.national.com/ds/LM/LM2825.pdf
will do it in one chip!

That's not a chip, it's a 1A dc-dc converter module in a 24-pin
wide DIP package. And it's not cheap, $15 each (Newark #07B6243).
The adjustable version looks interesting (#07B6240), but no stock.

Thanks,
- Win

(email: use hill_at_rowland-dot-org for now)

 

[Winfield Hill]

Winfield Hill wrote...

Rich Grise wrote...

That's not a chip, it's a 1A dc-dc converter module in a 24-pin
wide DIP package. And it's not cheap, $15 each (Newark #07B6243).
The adjustable version looks interesting (#07B6240), but no stock.

Worse, $24 at Avnet, with a 12-piece minimum-quantity requirement.

Thanks,
- Win

(email: use hill_at_rowland-dot-org for now)

 

[Winfield Hill]

Winfield Hill wrote...

Rich Grise wrote...

That's not a chip, it's a 1A dc-dc converter module in a 24-pin
wide DIP package. And it's not cheap, $15 each (Newark #07B6243).
The adjustable version looks interesting (#07B6240), but no stock.

Ah, DigiKey stocks the adjustable version, p/n LM2825N-ADJ-ND, $15.
4.5V to 40V in, set Vout 1.25 to 8V, up to 1A, 1.1V dropout. Nice.

Thanks,
- Win

(email: use hill_at_rowland-dot-org for now)