Breadboarded 74HCT7046 PLL very unstable

[Philip Pemberton]

Hi guys,

I'm trying to recover the bit clock from a 6.9375MHz NRZ bit stream. To
make things easier, this stream has several encoding rules:
- Thanks to the use of parity bits (each 7-bit data byte has an odd
parity bit in the LSB), the longest possible sequence with no transitions
is 14 bits long (the Clock Cracker: 1111 1110 0111 1111, repeated until
the end of the packet).
- All packets begin with a 2-byte clock run-in (CRI) and framing
sequence. This sequence (including sync) is: 10101010 10101010 11100100.

By my reckoning this means:
- There must be at least one transition every 14*(1/6.9375e6) = 2.02 us.
- Transitions can follow one after the other, as seen in the CRI - Thus
the time between two transitions can range from 144ns to 2.02us.

What I'm trying to do is put together a PLL-based clock recovery circuit,
using a 74HCT7046. I need it to start capturing at the CRI, and ideally
lock within 16 bits or less (or at least lock well enough to shift in and
match the frame sync byte).

I've breadboarded a test circuit using a Texas Instruments CD74HCT7046A,
1% metal film resistors and ceramic disc capacitors (the round brown
ones).

The component values I'm using are:
R1 = 33k
R2 = 10k
C1 = 100pF

And for the filter:
Series resistor between PC2OUT and VCOIN = 18k Capacitor from VCOIN to
ground = 120pF t1 = 2.16us
1/t1 = 462962us

.... but despite all my calculations (a dozen or so sheets of A4, loads of
Post-it notes, and a good few pages of my lab notebook!) saying "this will
work", I can't get the little swine to lock! Somehow the frequency always
ends up lower than it should, and the phase detector just won't push the
frequency any higher.

Given a static input voltage (VCO_in), the VCO frequency jitters quite
badly. If I turn off the trigger delay, the signal looks reasonably good.
Add in a 1us delay (that is, the scope starts displaying 1us after the
trigger) and you can see the square-wave VCO output jumping left and right
on the screen.

I do have a backup plan: a 13.875MHz crystal, in a 74HCT04 CMOS oscillator
circuit (the "buffered crystal oscillator" described by Rakon in one of
their application notes), with a BB419 varactor tacked on for frequency
control. The catch is that this requires a 0-20V input signal for the
varactor, which means I need to add an opamp (to boost the 0-5V signal
from the '7046's loop filter), a 20V power supply, and a divide-by- two
(DFF wired to toggle) to get from 13.875MHz to 6.9375MHz. I'm not keen on
this plan, though... it adds a fair few extra chips to the board...

Does anyone have any suggestions? Are HCT7046s, HC7046s or 4046s known to
be unstable when built up on breadboards?

Does anyone know of any decent PLL design software, or any good books on
the subject? My usual reference (Art of Electronics 2ed) doesn't really go
into much detail, and neither does the TI datasheet... which is, frankly,
pretty crap.

Thanks,

 

[Jamie]

Hi guys,

I'm trying to recover the bit clock from a 6.9375MHz NRZ bit stream. To
make things easier, this stream has several encoding rules:
- Thanks to the use of parity bits (each 7-bit data byte has an odd
parity bit in the LSB), the longest possible sequence with no transitions
is 14 bits long (the Clock Cracker: 1111 1110 0111 1111, repeated until
the end of the packet).
- All packets begin with a 2-byte clock run-in (CRI) and framing
sequence. This sequence (including sync) is: 10101010 10101010 11100100.

By my reckoning this means:
- There must be at least one transition every 14*(1/6.9375e6) = 2.02 us.
- Transitions can follow one after the other, as seen in the CRI - Thus
the time between two transitions can range from 144ns to 2.02us.

What I'm trying to do is put together a PLL-based clock recovery circuit,
using a 74HCT7046. I need it to start capturing at the CRI, and ideally
lock within 16 bits or less (or at least lock well enough to shift in and
match the frame sync byte).

I've breadboarded a test circuit using a Texas Instruments CD74HCT7046A,
1% metal film resistors and ceramic disc capacitors (the round brown
ones).

The component values I'm using are:
R1 = 33k
R2 = 10k
C1 = 100pF

And for the filter:
Series resistor between PC2OUT and VCOIN = 18k Capacitor from VCOIN to
ground = 120pF t1 = 2.16us
1/t1 = 462962us

... but despite all my calculations (a dozen or so sheets of A4, loads of
Post-it notes, and a good few pages of my lab notebook!) saying "this will
work", I can't get the little swine to lock! Somehow the frequency always
ends up lower than it should, and the phase detector just won't push the
frequency any higher.

Given a static input voltage (VCO_in), the VCO frequency jitters quite
badly. If I turn off the trigger delay, the signal looks reasonably good.
Add in a 1us delay (that is, the scope starts displaying 1us after the
trigger) and you can see the square-wave VCO output jumping left and right
on the screen.

I do have a backup plan: a 13.875MHz crystal, in a 74HCT04 CMOS oscillator
circuit (the "buffered crystal oscillator" described by Rakon in one of
their application notes), with a BB419 varactor tacked on for frequency
control. The catch is that this requires a 0-20V input signal for the
varactor, which means I need to add an opamp (to boost the 0-5V signal
from the '7046's loop filter), a 20V power supply, and a divide-by- two
(DFF wired to toggle) to get from 13.875MHz to 6.9375MHz. I'm not keen on
this plan, though... it adds a fair few extra chips to the board...

Does anyone have any suggestions? Are HCT7046s, HC7046s or 4046s known to
be unstable when built up on breadboards?

Does anyone know of any decent PLL design software, or any good books on
the subject? My usual reference (Art of Electronics 2ed) doesn't really go
into much detail, and neither does the TI datasheet... which is, frankly,
pretty crap.

Thanks,

If that protocol is what It looks like to me or something close to it
(SLIP), you aren't going to lock a PLL to that. the frame of a packet is
not constant in time to start with..

You are seeing this problem with the lock because the frequency is
varying too much.. You are getting more lower shifts than higher shifts
in freq. If you had a 50% duty of both sides, it would lock in.. BUt
this isn't the case..

I haven't done this in years but back in the hay day of Packet Radio,
this was a very popular thing.. SLIP protocol.. How ever, your system
could be using variable width modulation.

Either of them isn't going to lock that well since it's obvious that
you are dealing with a fast signal..

I suppose if you were to pass your signal through a FF, you could even
the duty cycle. THis would most likely give you a more stable PLL but
it's still going to wander.

It would be nice if there was a known protocol that we could reference
from ?

That's my take on it..

Jamie

 

[Philip Pemberton]

If that protocol is what It looks like to me or something close to it
(SLIP), you aren't going to lock a PLL to that. the frame of a packet is
not constant in time to start with..

It's the UK Teletext signal -- per the 1976 BBC/IBA/BREMA specification
found at http://www.doc.ic.ac.uk/~ih/teaching/teletext/tt-spec/ .

The datastream itself is likely to be a fairly random mix of 0s and 1s
(it's a text stream with odd parity, and the magazine/page numbers are
pseudo-Hamming coded). The Clock Cracker is simply a test to make sure a
clock extractor can maintain a stable lock when faced with a worst case
scenario.

As for my breadboard, it's a white nylon K&S (or something like that).
Banana-plugs along the top for power, power rails along the top and
bottom, and the usual fare of 6-hole strips of contacts.

Thanks,
Phil.

 

[Philip Pemberton]

How does the system idle between packets? Are the packets stacked
immediately after one another?

Typically you get one or two packets in the VBI, then nothing for the
visible video time. You'll get maybe 2 packets at a 64us interval, then
nothing for (64*310)us -- 310 lines of either visible data or other VBI.

Thanks,
Phil.

 

[Jan Panteltje]

Yup. Phase detectors don't like missing transitions. I did the
following 27 years ago for a floppy clock and data extractor...

http://analog-innovations.com/SED/ShiftRegisterPLL.pdf

Mine does not mind missing pulses, will stay on frequency, actually uses a 4046, and is dated 23-7-1984, makes it about 26 years ago.
Still working to this day:
ftp://panteltje.com/pub/fdc-2.jpg

The trick is 2 fold here, using sample and hold in the phase comparator:
first only open the sample gate when there is a pulse (say signal),
second the width of the pulse sets the gain, no analog ramps involved.

 

[Philip Pemberton]

Yup. Phase detectors don't like missing transitions. I did the
following 27 years ago for a floppy clock and data extractor...

Bah! Explanation sought and given...

But I'm not feeding the data straight into the PLL's comparison-signal
input. I'm feeding it through a string of six 74HCT04 gates to delay the
data signal, then XORing delayed_data with original_data to get a 25ns
pulse for each data line transition.

Unfortunately it seems this still isn't enough

Thanks,
Phil.

 

[Philip Pemberton]

Mine does not mind missing pulses, will stay on frequency, actually uses
a 4046, and is dated 23-7-1984, makes it about 26 years ago. Still
working to this day:
ftp://panteltje.com/pub/fdc-2.jpg

"Connection failed: the connection to the server was reset while the page
was being loaded."

I get the feeling I'm going to have to model the behaviour of the
HCT7046's phase comparator under a missing-pulse situation...

 

[Philip Pemberton]

Mine does not mind missing pulses, will stay on frequency, actually uses
a 4046, and is dated 23-7-1984, makes it about 26 years ago. Still
working to this day:
ftp://panteltje.com/pub/fdc-2.jpg

"Connection failed: the connection to the server was reset while the page
was being loaded."

I get the feeling I'm going to have to model the behaviour of the
HCT7046's phase comparator under a missing-pulse situation...

 

[Jan Panteltje]

"Connection failed: the connection to the server was reset while the page
was being loaded."

Works fine here, I see about 7 accesses that all worked in the log,.

 

[Philip Pemberton]

It's a clock recovery circuit, so he can't use the phase-frequency
detector.

Um.. I was using the PFD. Why can't I use it?

Something to do with the lack of phase-detect transitions when the loop
is locked and there's no input signal?

Thanks,

 

[Philip Pemberton]

Works fine here, I see about 7 accesses that all worked in the log,.

Working fine here now; must have been my 3G modem playing silly beggars.

Thanks,

 

[Philip Pemberton]

Oh, that's a crappy breadboard to use in the MHz frequencies. They're
OK at audio frequencies if you're careful about grounding and don't mind
troubleshooting the almost inevitable bad connection. But while it is
possible* to use them at higher frequencies, dead-bugging the circuit
over a ground plane will get you more joy.

Am I right in thinking that this applies to Stripboard (aka Veroboard)
too?

For those who haven't seen it -- stripboard is an FR2 (phenolic) board
with holes on a 0.1in (2.54mm) grid, and wide (about 10-20mil shy of
fully shorted) copper tracks running horizontally across. You cut tracks
and add wires to route the signals around.

I'll have to have a play with "manhattan" / deadbug construction later
this week. In the meantime, I think I might order some low-value 0805-
size NP0/C0G ceramic capacitors to play with...

Thanks,

 

[Philip Pemberton]

If it's VBI data, a VCXO-based PLL is probably more appropriate than an
RC oscillator-based one.

OK, that would be Design Variant #2 -- I had a 13.875MHz crystal rigged
up in a HCT04-based buffered TTL oscillator circuit, with a BB419 varactor
tied in to shift the frequency based on an incoming voltage. Catch is,
this voltage needs to go to 20V to get the BB419's capacitance low enough
to go much over 13.875. If memory serves, the frequency varied from about
13.850 to 13.900MHz over a range of 0V to 20V in.

Thanks,

 

[Jan Panteltje]

Am I right in thinking that this applies to Stripboard (aka Veroboard)
too?

For those who haven't seen it -- stripboard is an FR2 (phenolic) board
with holes on a 0.1in (2.54mm) grid, and wide (about 10-20mil shy of
fully shorted) copper tracks running horizontally across. You cut tracks
and add wires to route the signals around.

Z80 board 4 MHz on 2.54 mm eurocard:
ftp://panteltje.com/pub/s/wiring2.jpg

18 MHz:
ftp://panteltje.com/pub/z80/graphics_card_bottom.jpg
ftp://panteltje.com/pub/z80/graphics_card_top.jpg

38 MHz video ADC DAC connected to a 50 MHz FPGA board:
ftp://panteltje.com/pub/2h/alles2.jpg

64 MHz PIC, bu tinternal clock at 8MHz:
http://panteltje.com/panteltje/pic/scope_pic/lcd_rear_img_2004.jpg
http://panteltje.com/panteltje/pic/io_pic/io_pic_pcb_top_img_1827.jpg
http://panteltje.com/panteltje/pic/io_pic/io_pic_pcb_bottom_2_img_1829.jpg

I think you should only worry above 200 MHz or so on veroboard.
I have build TV modulators on it.
With normal resistors, not SMD.

Just use common sense when wiring it and in the layout.

 

[Philip Pemberton]

Yup. Miss a transition --> loop unlocks.

Rats.

I have found a nice PDF with some notes on phase detectors and clock
recovery:

http://paulo.moreira.free.fr/microelectronics/padova/padova.htm

Moreira, Paulo. Introduction to Integrated DLLs and PLLs.

The one I'm referring to is "PLL Applications". Pages 6 onwards explain
the Hogge, Alexander and Modified Triwave phase detectors. I think I
might have a go at building a Hogge detector in a bit and see if that
works any better...

And the VCXO is going back in too, if only because it's more stable than
the RC VCO and has a more useful frequency range...

Thanks,

 

[Philip Pemberton]

If memory serves, the frequency
varied from about 13.850 to 13.900MHz over a range of 0V to 20V in.

Just tested again with a new build of the circuit. Centre frequency is
13.875MHz. With the varactor input grounded I get 13.8748MHz, and with it
wired to 5V I get 13.8753MHz.

Looks like I might not need the amplifier and 20V supply after all.

 

[[email protected]]

Generally yes... although there *are* boards like that out there that *do*
have a complete plane (punctuated by the "signal" holes -- which are all
isolated; sometimes you'll get a few busses down the edge of the board,
though) on one or both sides.

They tend to be rather more expensive than the "regular" type of board,
though... mostly due to low volumes, I expect, since it doesn't seem like it
should cost anything more to produce them!


Dead bug construction on a solid copper plane -- using donuts, Kapton tape, or
similar to create small isolated islands when needed -- works quite well.

X-acto knives do a great job on copperclad. Do be careful, though.

 

[Philip Pemberton]

With a 7046? You'd need a trimpot to get it close enough to lock, and a
little temperature change would probably push it out of lock range.

No, I've torn the original design up and started over. I now have:

- A Hogge phase detector, built from a HCT74 D-flip-flop, a HCT86 XOR
and a HCT125 O/C buffer
- A HCT04-based TTL oscillator with a BB419 varactor providing the VCO
functionality
- An R/C loop filter (currently 30k series R, 100pF capacitor to
ground; they were sitting on my desk and seem to work)

I need to look at the loop filter -- I suspect I need an opamp buffer for
the VCO (the frequency is a little off when the loop is 'locked'), and
I'm willing to bet the filter's cutoff frequency (if not its entire
design) is completely non-optimal.

 

[Philip Pemberton]

An op amp lead-lag filter is the simplest kind you should consider for a
clock recovery job, where keeping the eye diagram open requires careful
control of the peak phase error.

OK, that's fair enough, but how do I go about selecting suitable
component values?

For a basic 2-resistor-1-capacitor lead-lag network (per
www.minicircuits.com/pages/pdfs/vco15-10.pdf page 4), there are two time
constants, produced from the component values. Alternatively I can work
backwards and use the time constants to come up with component values (by
plugging in a value for e.g. C1 and extracting R1 and R1+R2 then working
backwards to get R2 from that).

But what do I set the time constants to? How do I know it's working?

I also found a PLL design tool at http://www.aubraux.com/design/pll-
design-tool.php, but that asks for:
Phase detector gain
VCO gain
Loop bandwidth
Damping factor
Divider value
Scaling resistor

"Are you sure you know what you're doing?"
"Not even close."

Thanks,
Phil.

 

[Baron]

Jim Thompson Inscribed thus:

Good question. I once had one that also drilled a hole in the pad,
for thru-hole. I'd love to find another!

...Jim Thompson

Yes, me too ! When you do let me know I used to have a set of
three of them, different sizes, heavens knows where they disappeared
to...