Audio phase lock loop design info

[Jorgito]

Hi All,

Looking for basic design reference info for audio phase lock loops. For
example, given a specified analog input S/N, what acquisition time is needed
to achieve 1 degree phase resolution?

Thanks.

Jorgito

 

[MooseFET]

Hi All,

Looking for basic design reference info for audio phase lock loops. For
example, given a specified analog input S/N, what acquisition time is needed
to achieve 1 degree phase resolution?

Acquisition time and S/N doesn't lead directly to phase accuracy. A
great deal depends on the type of phase detector you are using. The
initial locking process is very nonlinear. Once you get past that,
the situation is often linear enough that a simple linear model of the
situation works. The noise near the signal ends up mattering more
than that far away.

What roughly is your SNR?
What sort of phase detector are you planning on using?

It is a fairly common practice to make the filter part of the PLL
change so that you get a quick lock and initial settling and then
later enough low passing to get the needed noise rejection.

 

[Jorgito.]

Hello, thanks for replying.

My signal of interest is a continuous 20 kHz analog tone. The S/N will be >
50 dB. I have several seconds or more to lock. I'd like to be able to
measure the phase to better than one degree. Can you recommend an approach?

Thanks again,
Jorgito

 

[MooseFET]

Hello, thanks for replying.

My signal of interest is a continuous 20 kHz analog tone. The S/N will be >
50 dB. I have several seconds or more to lock. I'd like to be able to
measure the phase to better than one degree. Can you recommend an approach?

50dB -> 1:316

arcsin(1/316) = 0.2 degrees

Life is good. I'm not even sure you need the whole PLL.

Your 1 degree measurement suggests that you have a reference signal
and a signal to be measured. Is this the case or are you looking to
detect a 1 degree modulation of a signal.

The flip-flop phase detector in a 4046 will settle to 1 degree of
error quite quickly. For small phase errors, the detector plus
resistor can be simplified to be considered as a current source in the
math. For small on times, the effective value of the resistance is
very high so the math gets a lot easier.

 

[Tam]

50dB -> 1:316

arcsin(1/316) = 0.2 degrees

Life is good. I'm not even sure you need the whole PLL.

Your 1 degree measurement suggests that you have a reference signal
and a signal to be measured. Is this the case or are you looking to
detect a 1 degree modulation of a signal.

The flip-flop phase detector in a 4046 will settle to 1 degree of
error quite quickly. For small phase errors, the detector plus
resistor can be simplified to be considered as a current source in the
math. For small on times, the effective value of the resistance is
very high so the math gets a lot easier.

If I did this right, 1 degree at 20 KHz is about 140 ns. A PLL should easily
have a ststic error less than 1/10 of that.

Tam

 

[MooseFET]

[... moved to bottom where it belongs ...]

Hi All,
Looking for basic design reference info for audio phase lock loops.
For
example, given a specified analog input S/N, what acquisition time is
needed
to achieve 1 degree phase resolution?
Acquisition time and S/N doesn't lead directly to phase accuracy. A
great deal depends on the type of phase detector you are using. The
initial locking process is very nonlinear. Once you get past that,
the situation is often linear enough that a simple linear model of the
situation works. The noise near the signal ends up mattering more
than that far away.
What roughly is your SNR?
What sort of phase detector are you planning on using?
It is a fairly common practice to make the filter part of the PLL
change so that you get a quick lock and initial settling and then
later enough low passing to get the needed noise rejection.
Hello, thanks for replying.
My signal of interest is a continuous 20 kHz analog tone. The S/N will
be >
50 dB. I have several seconds or more to lock. I'd like to be able to
measure the phase to better than one degree. Can you recommend an
approach?

50dB -> 1:316

arcsin(1/316) = 0.2 degrees

Life is good. I'm not even sure you need the whole PLL.

Your 1 degree measurement suggests that you have a reference signal
and a signal to be measured. Is this the case or are you looking to
detect a 1 degree modulation of a signal.

The flip-flop phase detector in a 4046 will settle to 1 degree of
error quite quickly. For small phase errors, the detector plus
resistor can be simplified to be considered as a current source in the
math. For small on times, the effective value of the resistance is
very high so the math gets a lot easier.

If I did this right, 1 degree at 20 KHz is about 140 ns. A PLL should easily
have a ststic error less than 1/10 of that.

Yes, at least for a HC4046.

1/(20K * 360) = 138.888nS

Also tan(1) = 0.017

So you need a cut off frequency of about

20K / 0.017 = 1.2MHz so fairly normal op-amps will do.