Analog Device's AD1871 24 bit analog to digital converter

[[email protected]]

Hello,

Is anyone using Analog Device's AD1871 in their design? I'm trying to
use two of them in cascade mode and I'm finding bugs in the part, and
plenty of mistakes and deficiencies in the data sheet. The control
part and the audio data are both in cascade mode.

If anyone is using the part and specifically in cascade mode, could you
please tell me what you've seen and have you been able to get the part
to work correctly?

I've had a few discussions with the manufacturers and I'm not convinced
they've ever tested this part with the control port and the data port
both in cascade mode.

I'm very disappointed in the part and the documentation and I'm close
to designing out of the product.

Any help, advice or just share the problems you've had with the part
would be very helpful.

Thanks,
Dale

 

[Tim Shoppa]

I'm very disappointed in the part and the documentation and I'm close
to designing out of the product.

Any help, advice or just share the problems you've had with the part
would be very helpful.

Not that particular part, but in general for most recent-generation
serial-data-bus AD parts you really really have to make sure that
you're obeying the clock rise, fall, hold, and skew times.

A quick look at the AD1871 datasheet makes me see that they don't
specify rise/fall times. That makes it hard to obey them to the letter!
Wjhen daisy chaining things must get exponentially worse.

In my limited experience with their serial-control-bus DDS's, a typical
PIC or microcontroller resulted in flaky operation because the
rise/fall times of the serial bus clock being in the 3-4ns region was
way too long.

Tim.

 

[[email protected]]

Thanks for the reply Tim. I finally found the problem. The data sheet
has yet another mistake in it! The data sheet is worthless. Bit_Clk
high to low, not low to high clocks in the LRClk.

Dale

 

[John Larkin]

Thanks for the reply Tim. I finally found the problem. The data sheet
has yet another mistake in it! The data sheet is worthless. Bit_Clk
high to low, not low to high clocks in the LRClk.

The analog design guys tend to do truly bizarre digital interfaces,
then explain them badly and often just plain wrong. Timing diagrams
can be especially bad. They also don't like to distinguish between
edges and levels. "When LE goes high, data is transferred..." could
mean either, and usually does.


John