AGC circuit ... threshold amplifier question

[MRW]

I have this circuit:
http://tinypic.com/view/?pic=333cv43

I encountered this threshold amplifier circuit. I'm trying to
understand how it works. So far, it seems like it is just a summing
amplifier and op amp rectifier combined. I used superposition to find
out the voltage at the inverting input (V-), but after looking at the
mess of equations I still can't relate the functions of each
components.

I don't see how the circuit starts passing the signal when a certain
threshold level is met. I also do not understand the function of the
diodes and the capacitor if the signal source (VA) is supposed to be
DC.

Can anyone help?


Thanks!

 

[Andrew Holme]

I have this circuit:
http://tinypic.com/view/?pic=333cv43

I encountered this threshold amplifier circuit. I'm trying to
understand how it works. So far, it seems like it is just a summing
amplifier and op amp rectifier combined. I used superposition to find
out the voltage at the inverting input (V-), but after looking at the
mess of equations I still can't relate the functions of each
components.

I don't see how the circuit starts passing the signal when a certain
threshold level is met. I also do not understand the function of the
diodes and the capacitor if the signal source (VA) is supposed to be
DC.

Can anyone help?


Thanks!

It's an odd-looking circuit. Where did you encounter it? Not homework, I
hope?

Through the action of negative feedback, the voltage at V- (pin 2) is always
equal to the voltage at V+ (pin 3) i.e. 0V.

What you have is an integrator with output clamping diodes.

You spotted the summing network on the input. You have a fixed current
flowing into the summing node through R3 and R4, and a variable current due
to the input voltage. The voltage on the capacitor will either ramp up, or
ramp down, depending on the net current. When the capacitor voltage
reaches 0.7V, the clamping diodes start to conduct, bypassing the capacitor,
preventing the output voltage ramping further.

 

[MRW]

It's an odd-looking circuit. Where did you encounter it? Not homework, I
hope?

Greetings Andrew.

Sorry, it's not homework. It's one of those datasheet circuits that I
decided to simulate in SPICE, so I can compare my derived equations. My
equations were very basic and ideal. I was assuming a DC input so I
kept the capacitor open. I also made ideal diode assumptions (either
open or short) based on whether the input signal was positive or
negative. Not exactly the same method as SPICE.

Through the action of negative feedback, the voltage at V- (pin 2) is always
equal to the voltage at V+ (pin 3) i.e. 0V.

What you have is an integrator with output clamping diodes.

So the diodes are the components responsible for the "threshold" part?
I originally didn't see the diodes as clamping devices. I just thought
it looked like their function was to rectify a signal.

You spotted the summing network on the input. You have a fixed current
flowing into the summing node through R3 and R4, and a variable current due
to the input voltage. The voltage on the capacitor will either ramp up, or
ramp down, depending on the net current. When the capacitor voltage
reaches 0.7V, the clamping diodes start to conduct, bypassing the capacitor,
preventing the output voltage ramping further.

I guess that answers my question above. Thanks!

 

[Andrew Holme]

Greetings Andrew.

Sorry, it's not homework. It's one of those datasheet circuits that I
decided to simulate in SPICE, so I can compare my derived equations. My
equations were very basic and ideal. I was assuming a DC input so I
kept the capacitor open. I also made ideal diode assumptions (either
open or short) based on whether the input signal was positive or
negative. Not exactly the same method as SPICE.


So the diodes are the components responsible for the "threshold" part?

No, I would say the current through R3 and R4, which offsets the input, is
the threshold.

Please see my reply to my own post above for more comments.

 

[Andrew Holme]

I have this circuit:http://tinypic.com/view/?pic=333cv43

I encountered this threshold amplifier circuit. I'm trying to
understand how it works. So far, it seems like it is just a summing
amplifier and op amp rectifier combined. I used superposition to find
out the voltage at the inverting input (V-), but after looking at the
mess of equations I still can't relate the functions of each
components.

I don't see how the circuit starts passing the signal when a certain
threshold level is met. I also do not understand the function of the
diodes and the capacitor if the signal source (VA) is supposed to be
DC.

Can anyone help?

Thanks!

Looks like I was half-asleep last night. Let's try again:

You say this is an AGC threshold amplifier. I've not come across the
term "threshold amplifier" before. I'm guessing this circuit is
inserted in the feedback path of an AGC control loop; the input voltage
VA representing the received signal strength at the output of the
gain-controlled amplifier; and the stronger the signal, the more
negative VA becomes.

The threshold is set by the current fed into the summing node via R3
and R4. This threshold represents the desired maximum output. When
the signal exceeds this, the net input current at the summing node is
negative, the integrator output voltage rises until it is clamped at
+0.7V by D1. This control voltage commands minimum gain.

When the received signal is below threshold, the integrator output
heads negative, and it behaves as a low-pass filter with cut-off
frequency of 1600Hz and DC gain of 2, as I explained in one of my
earlier posts.

 

[MRW]

Looks like I was half-asleep last night. Let's try again:

I've been half-asleep most of the time.

You say this is an AGC threshold amplifier. I've not come across the
term "threshold amplifier" before. I'm guessing this circuit is
inserted in the feedback path of an AGC control loop; the input voltage
VA representing the received signal strength at the output of the
gain-controlled amplifier; and the stronger the signal, the more
negative VA becomes.

You are right that the threshold amplifier is part of the AGC loop.
However, VA is coming from the input signal instead of the output. Here
is the actual circuit from That Corp.:
http://tinypic.com/view/?pic=2vafpua . I wanted to analyze each section
one by one to understand it more.

The threshold is set by the current fed into the summing node via R3
and R4. This threshold represents the desired maximum output. When
the signal exceeds this, the net input current at the summing node is
negative, the integrator output voltage rises until it is clamped at
+0.7V by D1. This control voltage commands minimum gain.

So the output from the threshold amplifier is always going to be the
same value once the threshold is reached? I'm still not getting a good
grasp on how it acts to maintain the constant amplitude level at the
output.

When the received signal is below threshold, the integrator output
heads negative, and it behaves as a low-pass filter with cut-off
frequency of 1600Hz and DC gain of 2, as I explained in one of my
earlier posts.

I'm still trying to understand this portion. Did you use KCL for your
analysis? I tried doing superposition in finding the symbolic voltage
equations at the inverting input and I just got a mess of equations. I
know the opamp holds the inverting input voltage the same as the
grounded non-inverting input, but I figured if I find the voltage
equations at the inverting input, then I can relate VA and Vout easily.

 

[Andrew Holme]

You are right that the threshold amplifier is part of the AGC loop.
However, VA is coming from the input signal instead of the output. Here
is the actual circuit from That Corp.:http://tinypic.com/view/?pic=2vafpua.

OK, it's a lot easier to make sense of it from the full circuit ! My
previous guesses were not quite correct. So VA is a measure of the
input power, and there is no overall feedback loop.

So the output from the threshold amplifier is always going to be the
same value once the threshold is reached? I'm still not getting a good
grasp on how it acts to maintain the constant amplitude level at the
output.

When the input signal is below threshold, the output of U1D will sit at
+0.7V, D1 is reverse-biased, and gain is fixed. As the signal starts
to exceed the threshold, the output of U1D falls, D1 conducts, and gain
is progressively reduced. In this mode, U1D operates as a low-pass
filter with a DC gain of 2.

Did you use KCL for your
analysis? I tried doing superposition in finding the symbolic voltage
equations at the inverting input and I just got a mess of equations. I
know the opamp holds the inverting input voltage the same as the
grounded non-inverting input, but I figured if I find the voltage
equations at the inverting input, then I can relate VA and Vout easily.

If I didn't recognise the configuration as a low-pass filter, I would
write down the transfer function in terms of the Laplace operator 's',
and draw a Bode plot using scilab.

Download scilab from www.scilab.org and run the following code:

s = poly(0,'s');
C7 = 10e-9;
R13 = 4.99e3;
R2 = 10e3;
f = 1/ (s*C7 + 1/R2) / R13;
xset("window",0);xbasc(0);xselect();
set("figure_style","old");
bode(syslin('c', f), 10, 10e3, 0.01);

 

[Andrew Holme]

Please see my other post first; but now I have more time, let me own-up to
some of my earlier mistakes:


Wrong. The stonger the signal, the more positive VA becomes.

Wrong. When input is below threshold, the net summed input is negative, and
the output clamps at +0.7V. So this commands maximum gain.

Wrong. This happens when the signal is above threshold.

Let me also say something more about analysing the integrator circuit. When
you have an inverting amplifier with feedback resistor Rf and input resistor
Ri, gain is -Rf/Ri. Here, Rf is a complex impedance, comprising a resistor
and capacitor in parallel:

Zf = XC7 || R2

Xc = 1/(s*C7)

Zf = 1/ (s*C7 + 1/R2)

Gain = -Zf / R13

where 's' is the Laplace operator.

 

[MRW]

Please see my other post first; but now I have more time, let me own-up to
some of my earlier mistakes:

Thanks, Andrew!

So, using this as my reference circuit:
http://tinypic.com/view/?pic=333cv43

Here is what I got for the output voltage, Vo:

Vo = - (VA / [(sC2 + 1/R2) * R1]) - (VCC / [(sC2 + 1/R2)*R3]) - (VCC *
R5 - VCC * R6) / ([sC2 + 1 / R2]*[R5 + R6]*R4)

Does this look right?

I'm still trying to understand your earlier posts, but I think starting
out with an overall transfer function will help me. Thanks!

 

[Andrew Holme]

Please see my other post first; but now I have more time, let me own-up to
some of my earlier mistakes:Thanks, Andrew!

So, using this as my reference circuit:http://tinypic.com/view/?pic=333cv43

Here is what I got for the output voltage, Vo:

Vo = - (VA / [(sC2 + 1/R2) * R1]) - (VCC / [(sC2 + 1/R2)*R3]) - (VCC *
R5 - VCC * R6) / ([sC2 + 1 / R2]*[R5 + R6]*R4)

Does this look right?

No. Let me re-format your expression to show it more clearly. View in
a fixed-pitch font:

Vo = - (VA / [(sC2 + 1/R2) * R1])
- (VCC / [(sC2 + 1/R2) * R3])
- (VCC * R5 - VCC * R6) / ([sC2 + 1/R2] * [R5 + R6] * R4)

The current in R4 is Vcc/(R4+R6) - Vcc/(R4+R5)

The third line should be:

- (Vcc/[R4+R6] - Vcc/[R4+R5]) / [sC2 + 1/R2]

 

[Andrew Holme]

So, using this as my reference circuit:http://tinypic.com/view/?pic=333cv43

Here is what I got for the output voltage, Vo:

Vo = - (VA / [(sC2 + 1/R2) * R1]) - (VCC / [(sC2 + 1/R2)*R3]) - (VCC *
R5 - VCC * R6) / ([sC2 + 1 / R2]*[R5 + R6]*R4)

Does this look right?No. Let me re-format your expression to show it more clearly. View in

a fixed-pitch font:

Vo = - (VA / [(sC2 + 1/R2) * R1])
- (VCC / [(sC2 + 1/R2) * R3])
- (VCC * R5 - VCC * R6) / ([sC2 + 1/R2] * [R5 + R6] * R4)

The current in R4 is Vcc/(R4+R6) - Vcc/(R4+R5)

The third line should be:

- (Vcc/[R4+R6] - Vcc/[R4+R5]) / [sC2 + 1/R2]

Correction:

Current in R4 = I4 = VCC*(R5-R6) / ( R5*R6 + R4*R5 + R4*R6)

The third line should be:

- I4 / [sC2 + 1/R2]

 

[MRW]

Current in R4 = I4 = VCC*(R5-R6) / ( R5*R6 + R4*R5 + R4*R6)

The third line should be:

- I4 / [sC2 + 1/R2]

How did you get R5*R6? I just found the voltage, VC, between R5 and R6
using superposition and use that in part of my transfer function.
Thanks!

 

[Andrew Holme]

Current in R4 = I4 = VCC*(R5-R6) / ( R5*R6 + R4*R5 + R4*R6)

The third line should be:

- I4 / [sC2 + 1/R2]

How did you get R5*R6? I just found the voltage, VC, between R5 and R6
using superposition and use that in part of my transfer function.

View in a fixed-pitch font:


___
+Vcc .-----|___|--->--.
| R6 I6 |
/+\ |
( ) |
\-/ |
| ___ |
0V o-----|___|---<--o
| R4 I4 |
/+\ |
( ) |
\-/ |
| ___ |
-Vcc '-----|___|---<--'
R5 I5


Vcc = R6.I6 + R4.I4
Vcc = R5.I5 - R4.I4

I6 = (Vcc - R4.I4) / R6
I5 = (Vcc + R4.I4) / R5

I4 = I6 - I5
I4 = Vcc/R6 - R4.I4/R6 - Vcc/R5 - R4.I4/R5

R5.R6.I4 = R5.Vvcc - R5.R4.I4 - R6.Vcc - R6.R4.I4

I4.[R5.R6 + R5.R4 + R6.R4] = Vcc.[R5 - R6]