M
Mark
Hi All,
I have a question about ADCs, specifically high speed pipelined type (80MS/s
@ 12 bit).
Background: A signal is generated using a 14 bit DAC from some external
equipment, but only the upper 10 bits are used, and I have a 12 bit ADC to
receive it. I need to recreate a digital version of this analogue signal at
10 bits of resolution. I'm not worried that much about absolute accuracy,
but if the DAC produces a particular voltage then I need to sample this and
generate a clean digital output on successive samples.
The problem I see with this is difference in gain; the DAC gain could be
slightly different to my ADC gain. However I don't particularly care that a
sample might be seen as the same for two different input values or skip
values due to gain difference, the key concern is that successive samples of
the same input level must always be the same. If the output from the DAC
happens to be right at the quantisation point between two binary values of
my ADC, then I can foresee even very small levels of noise on the signal
causing my ADC to flip between the two states.
One solution to this might be to convert the binary output of my ADC to gray
code. Gray coding means that there would be a single bit change, and I could
detect which bit was changing and clear it - all other bits would then
remain stable. Then I could convert back to binary. As long as the noise is
below 1 LSB at 10 bits then I get the same successive samples.
Am I actually worrying about a problem that doesn't exist? Do ADCs have
'noise elimating' logic like this inside anyway? If not, anyone have a
general solution?
Thanks!
Mark.
I have a question about ADCs, specifically high speed pipelined type (80MS/s
@ 12 bit).
Background: A signal is generated using a 14 bit DAC from some external
equipment, but only the upper 10 bits are used, and I have a 12 bit ADC to
receive it. I need to recreate a digital version of this analogue signal at
10 bits of resolution. I'm not worried that much about absolute accuracy,
but if the DAC produces a particular voltage then I need to sample this and
generate a clean digital output on successive samples.
The problem I see with this is difference in gain; the DAC gain could be
slightly different to my ADC gain. However I don't particularly care that a
sample might be seen as the same for two different input values or skip
values due to gain difference, the key concern is that successive samples of
the same input level must always be the same. If the output from the DAC
happens to be right at the quantisation point between two binary values of
my ADC, then I can foresee even very small levels of noise on the signal
causing my ADC to flip between the two states.
One solution to this might be to convert the binary output of my ADC to gray
code. Gray coding means that there would be a single bit change, and I could
detect which bit was changing and clear it - all other bits would then
remain stable. Then I could convert back to binary. As long as the noise is
below 1 LSB at 10 bits then I get the same successive samples.
Am I actually worrying about a problem that doesn't exist? Do ADCs have
'noise elimating' logic like this inside anyway? If not, anyone have a
general solution?
Thanks!
Mark.