About the subthreshold swing in SOI CMOS

[Schmit]

For fully depleted SOI, some book says it can reach a nearly 60mV/Dec
swing because its effective gate depletion width is large. What does
"effective gate depletion width" mean ? I have only heard of "depletion
width" in a bulk CMOS. Is it a unique advantage of SOI ? I am
suspicious about it. If the depletion width (Wd) of bulk CMOS can be
made big enough, then the control coefficient m=1+3tox/Wd also can
approach 1.
Thanks for attention

 

[[email protected]]

Hi,

You may refer to this page:

http://www.kodkodkod.com/files/tutorial_fully_depleted_silicon_on_insulator.htm

Regards,

KodKodKod Learning Consulting - Here you get the answers

 

[Schmit]

I think I got the answer.
Thanks a lot.