a question (extreme newbie alert)

[Sean McIlroy]

hi all

this will be my first attempt at formulating a sensible question about
this stuff. you've been warned. here's the question...

unless i've already misinterpreted something (http://
webpages.ursinus.edu/lriley/ref/circuits/img96.gif) the following is
an NPN transistor NOT gate:

================================================================

-- V[B1] -- << R >> -- V[B1] -- << base >>

-- V[C1] -- << R[C] >> -- V[C1] -- << collector >>

<< ground >> --------------------- << emitter >>

================================================================

hence one has

V[C2]

= V[C1] - R[C] * I[C]

= V[C1] - R[C] * I * gain

= V[C1] - ( gain * R[C] / R ) * ( V[B1] - V[B2] )

but the webpage (http://webpages.ursinus.edu/lriley/ref/circuits/
node4.html) seems to be saying that there are m,b (m<0) with

V[C2] = m * V[B1] + b

perhaps V[B2] is fixed for reasons unknown to me?

peace
stm

 

[John Popelish]

hi all

this will be my first attempt at formulating a sensible question about
this stuff. you've been warned. here's the question...

unless i've already misinterpreted something

http://webpages.ursinus.edu/lriley/ref/circuits/img96.gif

the following is
an NPN transistor NOT gate:

================================================================

-- V[B1] -- << R >> -- V[B1] -- << base >>

-- V[C1] -- << R[C] >> -- V[C1] -- << collector >>

<< ground >> --------------------- << emitter >>

I can not parse what you intend by these strings of characters.

================================================================

hence one has

V[C2]

= V[C1] - R[C] * I[C]

= V[C1] - R[C] * I * gain

= V[C1] - ( gain * R[C] / R ) * ( V[B1] - V[B2] )

but the webpage (http://webpages.ursinus.edu/lriley/ref/circuits/
node4.html) seems to be saying that there are m,b (m<0) with

V[C2] = m * V[B1] + b

perhaps V[B2] is fixed for reasons unknown to me?

Vbe, the forward biased base to emitter junction is not a
fixed voltage, but varies over a small range for the normal
range of input currents between something like .5 and .7
volts. So the simplifying assumption is often that it is
about .6 volts. If the input voltage (Vin) is 5 volts, the
voltage across the base resistor,Rb, is roughly 5-.6=4.4
volts. So the base current is roughly 4.4/Rb. The current
gain of the transistor falls dramatically as the collector
voltage gets pulled down lower than the base voltage, but
the upper limit on the collector current is the current gain
times the base current. So the collector current must be
equal to or less than gain * (Vin-Vbe) /Rb.

Does any of this help at all?

 

[kell]

hi all

this will be my first attempt at formulating a sensible question about
this stuff. you've been warned. here's the question...

unless i've already misinterpreted something (http://
webpages.ursinus.edu/lriley/ref/circuits/img96.gif) the following is
an NPN transistor NOT gate:

================================================================

-- V[B1] -- << R >> -- V[B1] -- << base >>

-- V[C1] -- << R[C] >> -- V[C1] -- << collector >>

<< ground >> --------------------- << emitter >>

================================================================

hence one has

V[C2]

= V[C1] - R[C] * I[C]

= V[C1] - R[C] * I * gain

= V[C1] - ( gain * R[C] / R ) * ( V[B1] - V[B2] )

but the webpage (http://webpages.ursinus.edu/lriley/ref/circuits/
node4.html) seems to be saying that there are m,b (m<0) with

V[C2] = m * V[B1] + b

perhaps V[B2] is fixed for reasons unknown to me?

peace
stm

When using the transistor as an inverting buffer (NOT gate) you're
supposed to drive it into saturation, so there's no point using the
gain of the transistor to try to calculate collector current.
Collector current is determined, in effect, by the collector resistor;
voltage across the collector-emitter junction is minimal.
You're using the transistor as a switch, it's only ever either ON or
OFF.

Not sure if that addresses your question, which is kind of hard to
follow, but I did notice you used a gain calculation.

 

[Sean McIlroy]

Does any of this help at all?

i think so. i'd like to check if you don't mind. i'll start by
reproducing my diagram, this time with the voltages labelled
correctly:

================================================================

-- V[B1] -- << R >> -- V[B2] -- << base >>

-- V[C1] -- << R[C] >> -- V[C2] -- << collector >>

<< ground >> --------------------- << emitter >>

================================================================

here's what i intend by it:

*) the base of a transistor T is at voltage level V[B2] and is
connected to a resistor with resistance R. the other end of this
resistor is at voltage level V[B1]

*) the collector of T is at voltage level V[C2] and is connected to a
resistor with resistance R[C]. the other end of this resistor is at
voltage level V[C1]

*) the emitter of T is at voltage level zero.

hence the V[in] and V[out] of the webpage are respectively my V[B1]
and V[C2]. this is the best i can do by way of a diagram. sorry.

you seem to say that, to a decent approximation, V[be] = ( V[B2] - <<
ground voltage >> ) = V[B2] is indeed fixed; specifically V[B2] = 0.6.
consequently, if V[B1] = 5 then

( V[B1] - V[B2] ) = (5 - 0.6) = 4.4

and

I = ( 1 / R ) * ( V[B1] - V[B2] ) = 4.4 / R

so that

I[C] = gain * I = ( gain / R ) * ( V[B1] - V[B2] )

implying

( V[C1] - V[C2] ) = R[C] * I[C] = ( gain * R[C] / R ) * ( V[B1] -
V[B2] )

and hence

V[C2] = V[C1] - ( gain * R[C] / R ) * ( V[B1] - V[B2] )

is this (with standard disclaimers about how a model is just a model)
right so far? here are a couple other points you could clarify if you
don't mind:

i)

the forward biased base to emitter junction ... varies over a small range for the normal

range of input currents.

by "input current" you mean "base current", right? can you give me an
idea what is the "normal" range of input currents? (qualitative
conditions, if they exist, would likely be more helpful to me at this
point than quantitative ones.)

ii)

The current gain of the transistor falls dramatically as the collector

voltage gets pulled down lower than the base voltage.

this constitutes a different biasing condition, right?

peace
stm

 

[John Popelish]

Does any of this help at all?

i think so. i'd like to check if you don't mind. i'll start by
reproducing my diagram, this time with the voltages labelled
correctly:

================================================================

-- V[B1] -- << R >> -- V[B2] -- << base >>

-- V[C1] -- << R[C] >> -- V[C2] -- << collector >>

<< ground >> --------------------- << emitter >>

================================================================

here's what i intend by it:

*) the base of a transistor T is at voltage level V[B2] and is
connected to a resistor with resistance R. the other end of this
resistor is at voltage level V[B1]

*) the collector of T is at voltage level V[C2] and is connected to a
resistor with resistance R[C]. the other end of this resistor is at
voltage level V[C1]

*) the emitter of T is at voltage level zero.

Lots better!

hence the V[in] and V[out] of the webpage are respectively my V[B1]
and V[C2]. this is the best i can do by way of a diagram. sorry.

That's fine.

you seem to say that, to a decent approximation, V[be] = ( V[B2] - <<
ground voltage >> ) = V[B2] is indeed fixed; specifically V[B2] = 0.6.
consequently, if V[B1] = 5 then

( V[B1] - V[B2] ) = (5 - 0.6) = 4.4

and

I = ( 1 / R ) * ( V[B1] - V[B2] ) = 4.4 / R

so that

I[C] = gain * I = ( gain / R ) * ( V[B1] - V[B2] )

Make that a less than or equal to. If the collector to
emitter voltage approaches zero, the gain heads toward zero,
so if this I(c) calculation shows a drop across R(C) greater
than 5 volts, you just assume the collector to emitter
voltage is less than .6 volts (the transistor is saturated on).

implying

( V[C1] - V[C2] ) = R[C] * I[C] = ( gain * R[C] / R ) * ( V[B1] -
V[B2] )

and hence

V[C2] = V[C1] - ( gain * R[C] / R ) * ( V[B1] - V[B2] )

is this (with standard disclaimers about how a model is just a model)
right so far? here are a couple other points you could clarify if you
don't mind:

All that assumes that the transistor does not get saturated
on by this collector current through the collector resistor.
But it wouldn't be a very good not gate if the transistor
dropped a significant part of the supply and the collector
resistor only dropped a part of it.

i)

range of input currents.
Right.

by "input current" you mean "base current", right?
Right.

can you give me an
idea what is the "normal" range of input currents? (qualitative
conditions, if they exist, would likely be more helpful to me at this
point than quantitative ones.)

The transistor gain curve versus collector current (at some
fixed small voltage collector to emitter , like 5 volts, is
often shown on the data sheet. There us usually some
collector current that exhibits the highest point on the
gain curve. For all collector currents with gain at least
half of that peak gain current point, the base to emitter
voltage will vary from about .5 to .7 volts. This is about
the normal linear gain range of that particular transistor.
Here is an example data sheet pulled at random to talk about:
http://www.onsemi.com/pub/Collateral/2N3906-D.PDF

Note figure 13, the current gain curve, with 1 volt
collector to emitter (in this case, since this is a
transistor designed for saturated switching, like your not
gate). At 25C, the peak gain (normalized to a multiplier of
1 on this graph) occurs at about 10 mA of collector current.
It falls to .5 at about 50 mA. The low current end of the
scale doesn't go low enough to find the low current
equivalent gain point. But you can pretty well assume that
if the transistor still has a little collector voltage, its
base to emitter drop will be in the range I have said. Once
the collector voltage falls below the base voltage, the base
voltage rises from the high base current it takes to drive
the collector hard into saturation. Figure 13 shows the
actual base to emitter voltage at various saturated
collector currents with the base current driven all the way
to 1/10th of the collector current, effectively saturating
the transistor till the current gain falls to 10. There is
also a curve with the collector voltage forced to 1 volt,
which drops the base voltage a little. But 1 volt is low
enough that the current gain is already falling a little, so
the base voltage is on the high end of what I have been
estimating. Saturated switching needs extra base to emitter
voltage, compared to linear amplification applications.

ii)

voltage gets pulled down lower than the base voltage.

Right. The gain is a process of diffusion of charges that
are drifting along a very thin base layer, and if they
wobble over into the reverse biased base to collector
junction, the electric field of this reverse biased junction
efficiently sweeps those charge carriers out to the
collector terminal. Once that junction becomes forward
biased, the internal electric field tends to head the charge
carriers in the junction back toward the base, so they show
up as increased base current, instead of increased collector
current, hence, lower current gain.

this constitutes a different biasing condition, right?

Yes. That bias condition is called "saturated on" or just
saturated.