Im working on a project and I need some help so if you have any
experience in this subject matter i dont mind that you speak your mind
with your ideas. I greatly appreciate it.
7 Segment Display Using Xilinx XC95108 CPLD Board
As shown in the class, a CPLD board used in our laboratory has been
used to display a counter output. This project is asking you to use
your knowledge in the ELEN 327 course and the experience you
accumulated in ELEN 328 to design a circuit, which is able to drive
the display on the Xilinx XC95108 CPLD board and show the exact
demonstration.
Things that concerned:
1. Design a counter that counts the cycle of even decimal numbers
only, starting from 0, 2, 4, ... to 20 and restarts from 0 again. You
can use any kind of flip-flop circuits, such as D-type, T-type, or JK
flip-flop.
2. Design a decoder, which decodes the output of a binary counter, and
translate it into a seven segment driver. Since the counter starts
from 0, ends at 20 and starts from 0 again, you need two 7-segment
display to show it. The actual pin connection information about these
two 7-segment display is at the end of your laboratory book.
3. Clock divider, which uses the high-speed crystal oscillator as the
source. The frequency of the crystal oscillator on our CPLD board is
4 MHz. You need to reduce this frequency in order for our eyes to
identify the counter output. You can also call this clock divider as
a speed controller. If you adjust the speed right, this display can
be a normal wall clock.
The block diagram of this design is shown below:
Crystal Oscillator------->Clock Divider------>Even Counter--------
experience in this subject matter i dont mind that you speak your mind
with your ideas. I greatly appreciate it.
7 Segment Display Using Xilinx XC95108 CPLD Board
As shown in the class, a CPLD board used in our laboratory has been
used to display a counter output. This project is asking you to use
your knowledge in the ELEN 327 course and the experience you
accumulated in ELEN 328 to design a circuit, which is able to drive
the display on the Xilinx XC95108 CPLD board and show the exact
demonstration.
Things that concerned:
1. Design a counter that counts the cycle of even decimal numbers
only, starting from 0, 2, 4, ... to 20 and restarts from 0 again. You
can use any kind of flip-flop circuits, such as D-type, T-type, or JK
flip-flop.
2. Design a decoder, which decodes the output of a binary counter, and
translate it into a seven segment driver. Since the counter starts
from 0, ends at 20 and starts from 0 again, you need two 7-segment
display to show it. The actual pin connection information about these
two 7-segment display is at the end of your laboratory book.
3. Clock divider, which uses the high-speed crystal oscillator as the
source. The frequency of the crystal oscillator on our CPLD board is
4 MHz. You need to reduce this frequency in order for our eyes to
identify the counter output. You can also call this clock divider as
a speed controller. If you adjust the speed right, this display can
be a normal wall clock.
The block diagram of this design is shown below:
Crystal Oscillator------->Clock Divider------>Even Counter--------
