555 Timer Discharge Pin 7 Question..

[Enigma]

Hello guys its me again.

Im getting conflicting information on the net about Pin 7 and its Discharge action.

From my understanding the Pin is there as an internal path to discharge the capacitor once Output Pin 3 goes LOW. This would mean that V+ is applied to the base of the discharge transistor to activate it. Ive read that V+ is applied when the OUTPUT goes HIGH but this would mean the transistor turns off when the OUTPUT goes LOW meaning that when discharge is supposed to occur the transistor would be OFF???
Im very confused as I can clearly see, hear and measure the discharge action when the OUTPUT goes LOW...?

(I can see the lights {green=output HIGH & red=output LOW}, hear the clicking of the speaker on output and I have a multimeter measuring Voltage across the resistor on the PIN 7 to V+) I can attach a pic if this is confusing.
Big Thanks

 

[BobK]

The discharge transistor is on when the output is low. You can see this in the block diagram in the datasheet. The base of the discharge transistor is connected to an inverter which is the output. So when the inverter input is high the discharge transistor is on and the output is low.

Bob

 

[Enigma]

Of Course!!! Amazing! I had to learn about 'inverters' to understand what is going on in this part of the circuit and now it makes perfect sense.
When the Q is HIGH it swtiches on the transistor and the inverter makes the output LOW and when the Q is LOW it swtiches OFF the transistor and the inverter makes the output go HIGH!
Thank You BobK.
p.s - why is it called an OUTPUT BUFFER and not an INVERTER/NOT GATE?

 

[BobK]

An output buffer increases the drive current available. In this case it is an inverting output buffer.

Bob

 

[Enigma]

Thanks BobK