February 05, 2020 by Asma Arooj
Nanotechnology and the minimal sizing of circuit designs is known as a major breakthrough in electronics development.
Minimal circuit complexity and sizing creates more space on a chip, causing it to work faster and more efficiently. In this article, we focus on a research project conducted by Purdue University and the Georgia Institue of Technology. The research partnership resulted in the development of a new type of transistor that holds more information than ever—with less space.
Neuromorphic systems hold promise for training and running neural networks more efficiently and running AI models faster than traditional CPUs and GPUs. (pictured: A neuromorphic chip developed by Stanford University).
Neuromorphic chips are designed specifically to perform more energy-efficient tasks. With the original idea of combining two devices together or aligning them next to each other, the Purdue University engineering team devised a method where tiny switches were used as transistors for storing the information as one device instead of two or more connected devices.
Integrating two devices to process as one has been the talk of electronics’ world for decades. Multiple attempts were made but there were interface issues between silicon and ferroelectric material. The researchers also demonstrated that the operation of ferroelectric RAM as a separate on-chip unit is a constraint that limits the potential efficiency of computing and its respective designs. To overcome the issues between silicon and ferroelectric material, the Purdue team devised a workaround with the help of the Georgia Institute of Technology.
The team developed a device that used a semiconductor possessing ferroelectric properties. The breakthrough in their method was the integration of two materials into one with the intention of avoiding interface issues. They used a conventional way of building the transistor but the result that came up using the newly proposed method produced a ferroelectric semiconductor field-effect transistor.
The material alpha indium selanide was used to develop the semiconductor carrying ferroelectric properties. This material was not only used due to its ferroelectric properties but also overcomes the problem of interface issues.
Conventional ferroelectric materials acted as an insulator in most cases instead of a semiconductor. The insulator has a wide bandgap, which resulted in the inability for electricity to pass through it, as well as no computing capabilities. However, the semiconductor material (i.e. alpha indium selenide) used by the research team consisted of a much smaller bandgap and this made the material act as an ideal semiconductor without losing ferroelectric properties.
The function of the new fabricated transistor using Purdue University’s research delivered better performance levels. The transistor was developed using a method that yielded better performance when compared to the conventionally fabricated ferroelectric field-effect transistors. Furthermore, it exceeded the expected optimization parameters.
The chip was optimized using an original technique by the research team, "ferroelectric tunneling junction." Where alpha indium selenide is integrated into space on a chip.
According to previous experiments, it was difficult to fabricate ferroelectric tunneling junction that yielded in high performance. The major reason behind it is the presence of wide bandgaps in traditional interface materials.
The ferroelectric semiconductor field-effect transistor developed by Purdue University researchers and Georgia Institute of Technology. Image Credit: Purdue University
On analyzing the use of alpha indium selenide, it was found that with a smaller bandgap, the material can be just 10 nanometers thick. The minimal thickness allows more current to flow through the substrate as compared to the thick material with a wide bandgap where no electrical current passed through it.
Researchers concluded that increased current flow to an area of a device gets scaled down to several nanometers. Scaling down the material makes the chips denser and also makes them more energy efficient. With the thinner material, even if it's of atomic layer thickness, electrodes on either sides of a tunneling junction can be much smaller as well.
Developed by Carver Mead, the concept of neuromorphic computing chips goes back to the 1980s. The concept of neuromorphic computing was very promising for the world of electronics. It gradually has taken over traditional computing systems because neuromorphic techniques parallel the adaptive learning process and computation.
Different research studies show that the use of ferroelectric materials are promising in the use of neuromorphic chips. They create a non-volatile multilevel memory effect in neural network hardware. When it comes to adaptive learning effects present in ferroelectric polarization, it reduces the circuit overhead of CMOS, which has an amplifier, integrator and activation function.
Ferroelectric materials overcome issues that are in conjunction with the processing of CMOS and device structure. The ferroelectric tunnel junctions imply to the employment of high-performance electronic synapses and the respective designing. Neuromorphic chips based on ferroelectric materials also show outstanding functions through ferroelectric domain switching.
Therefore, the development of a new type of transistor with the integration of ferroelectric RAM would eventually solve the traditional old challenges that engineers are facing for decades in case of devices consuming more space in a circuit design. The aim of this research is the development of more feasible methods where transistors and memory units are combined on a single chip. It was all about making computing faster and more efficient.
