March 02, 2020 by Luke James
At the IEEE Solid-State Circuits Conference (ISSCC) in San Francisco last month, French research organisation CEA-Leti debuted its 96-core processor made out of six individual chiplets.
Although we are constantly seeing more innovation being made with system-on-chip (SoC) technologies – a trend which has lasted decades and powers many of today’s most advanced computers – the idea is beginning to be eroded by cost and complexity. As a result, we are now more commonly witnessing advanced processors come to market that consist of a collection of individual chiplets in a single package that are bound together by high-bandwidth connections. AMD’s Zen 2 processor family is one example.
Now, French research organisation CEA-Leti, which has previously collaborated with leading semiconductor manufacturers such as STMicroelectronics, has shown us just how far chiplets can go by creating a 96-core processor made out of six of them.
3D Integration architectures for the 96-core processor. Image Credit: CEA-Leti.
The company’s prototype features 96 computing cores organised in six chiplets, each fabricated using a 28nm FDSOI manufacturing process. The chiplets are 3D-stacked in a face-to-face configuration that uses 20-micron pitch micro-bumps onto an active interposer embedding through-silicon vias (TSVs) in a 65nm technology node.
This active interposer technology overcomes limitations created by a lack of long-distance chiplet-to-chiplet communications and smooth integration of heterogenous chiplets by enabling integration of some active CMOS circuitry.
The interposer contains both voltage regulation circuits and a network that links the various parts of the core’s on-chip memories together. According to Pascal Vivet, a scientific director at CEA-Leti, active interposers are the best way forward for chiplet technology if it is ever to allow for multiple chiplet vendors to be integrated into systems.
“If you want to integrate chiplets from vendor A with chiplets from vendor B, and their interfaces are not compatible, you need a way to glue them together,” he says. “And the only way to glue them together is with active circuits in the interposer.”
The interposer, which features a network-on-chip, uses three different communication circuits that link the core’s on-chip SRAM memory. L1 and L2 caches, which are the fastest-access memories, are linked directly with no additional circuitry. The next-highest level of cache connections, L2 to L3, require additional networking built into the interposer, as does the link between L3 and off-chip memory.
Overall, the 96-chip system can achieve 3 terabytes per second per mm2 of silicon with a latency of only 0.6 nanoseconds per millimetre.
A product image of CEA-Leti's processor with 6 3D-stacked chiplets. Image Credit: CEA-Leti.
Many are hopeful that chiplet technology like that of CEA’s could reimagine the SoC industry, paving the way for chiplets from multiple vendors all with the ability to be easily integrated with little effort on standardized interfaces.
Although this result would mean cheaper, more powerful, more flexible systems that can be mixed and matched to individual specifications, we are not there yet.
Unlike CEA-Leti’s prototype system, commercial systems that rely on chiplets use silicon interposers. These have no active embedded circuitry and many instead rely on organic circuit-board material as opposed to silicon. These require a large amount of codesign between the chiplets and the integrating package.
Still, Vivet is hopeful that active interposer technology similar to that unveiled in CEA-Leti’s research will be an enabler of integrated heterogeneous functions. He added that chiplet-based ecosystems would now be rolled out rapidly in the high-performance computing sector and others such as automotive.
In the future, CEA-Leti will focus on addressing die-to-wafer hybrid bonding technology. This offers denser 3D interconnects with better electrical, mechanical, and thermal parameters.
