February 01, 2020 by Luke James
At December’s IEEE International Electron Devices Meeting, imec, a world-leader in nanoelectronics and digital technologies, demonstrated an in-depth study of scaled transistors with MoS2 and best device performance to date.
As demonstrated at December’s IEEE International Electron Devices Meeting, imec has fabricated nanoscale transistors with MoS2 – molybdenum disulfude – a 2D material that is classified as a transition metal dichalcogenide.
The demonstration confirmed theoretical findings in the company’s research and showed promising performance that supports the assertion that they could be used to replace today’s FinFETs and continue transistor scaling.
MoS2 is one of many 2D semiconductor materials. It has a thickness of three 0.6nm atomic monolayers. At IEEE’s annual International Electron Devices Meeting (IEDM), imec’s research was presented as an in-depth study of highly scaled MoS2-based transistors.
According to imec at the IEDM, the company’s research and findings confirm that there is great potential for the use of 2D materials for ultra-scaled transistors in both high-performance logic and memory applications. This is because research has shown that they exhibit little short-channel effects when compared to silicon channel transistors. The fabricated devices also performed largely in accordance with TCAD simulations.
A TEM (transmission electron microscopy) picture of a double gated WS2 FET device. Image Credit: imec.
Although they are not yet at the same level as modern silicon devices, imec says that the company is hopeful and that they see a realistic path for further development and improvements that will include a reduction of defects and double-gated transistor architecture.
This was confirmed by Iuliana Radu, imec’s Director, who said, although still an order of magnitude away from Si transistors, their team has brought MOSFET devices into a realm where they show promising performance for future logic and memory applications.
To bridge this order of magnitude, they identified a path of systematic improvements, such as a further reduction of the gate oxide thickness, the implementation of a double-gated architecture, and further reduction of channel and interface defects. They are transferring this knowledge to the 300mm-wafer platform for transistors with 2D materials, which was announced at last year’s IEDM.
Imec’s research is an example of ongoing research initiatives into so-called ‘beyond silicon’ or ‘beyond-CMOS’ devices where 2D materials are just one option among many. It was also one of 24 different papers that imec submitted for 2019’s IEDM, with other works presented including a 2MB MRAM array.
At the time of writing, the front-runner is the gate-all-around (GAA) FET, also known as a nanosheet or nanowire transistor. It is an evolution of the 3D-channel FinFET transistor, Samsung has already announced that the company intends to adopt it at its 3nm node and TSMC is expected to introduce it in its 2nm process.
Returning to 2D materials, its potential has already been realized with one-of-a-kind transistors built on natural flakes of 2D materials, with theoretical studies recommending them as the perfect channel material for extreme transistor scaling.
